1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008,2011 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 struct board_specific_parameters {
13 u32 datarate_mhz_high;
20 * This table contains all valid speeds we want to override with board
21 * specific parameters. datarate_mhz_high values need to be in ascending order
22 * for each n_ranks group.
24 const struct board_specific_parameters dimm0[] = {
27 * num| hi| clk| cpo|wrdata|2T
28 * ranks| mhz|adjst| | delay|
43 * The two slots have slightly different timing. The center values are good
44 * for both slots. We use identical speed tables for them. In future use, if
45 * DIMMs have fewer center values that require two separated tables, copy the
46 * udimm0 table to udimm1 and make changes to clk_adjust and wrlvl_start.
48 const struct board_specific_parameters *dimms[] = {
53 void fsl_ddr_board_options(memctl_options_t *popts,
55 unsigned int ctrl_num)
57 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
62 printf("Wrong parameter for controller number %d", ctrl_num);
65 for (i = 0; i < CONFIG_DIMM_SLOTS_PER_CTLR; i++) {
69 if (i >= CONFIG_DIMM_SLOTS_PER_CTLR) /* no DIMM */
72 pbsp = dimms[ctrl_num];
74 /* Get clk_adjust, cpo, write_data_delay, according to the board ddr
75 * freqency and n_banks specified in board_specific_parameters table.
77 ddr_freq = get_ddr_freq(0) / 1000000;
78 while (pbsp->datarate_mhz_high) {
79 if (pbsp->n_ranks == pdimm[i].n_ranks) {
80 if (ddr_freq <= pbsp->datarate_mhz_high) {
81 popts->clk_adjust = pbsp->clk_adjust;
82 popts->cpo_override = pbsp->cpo;
83 popts->write_data_delay =
84 pbsp->write_data_delay;
93 printf("Error: board specific timing not found "
94 "for data rate %lu MT/s!\n"
95 "Trying to use the highest speed (%u) parameters\n",
96 ddr_freq, pbsp_highest->datarate_mhz_high);
97 popts->clk_adjust = pbsp_highest->clk_adjust;
98 popts->cpo_override = pbsp_highest->cpo;
99 popts->write_data_delay = pbsp_highest->write_data_delay;
101 panic("DIMM is not supported by this board");
105 /* 2T timing enable */