2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_86xx.h>
28 #include <asm/fsl_pci.h>
29 #include <asm/fsl_ddr_sdram.h>
33 #include <fdt_support.h>
34 #include <spd_sdram.h>
37 #include "../common/pixis.h"
39 void sdram_init(void);
40 phys_size_t fixed_sdram(void);
41 void mpc8610hpcd_diu_init(void);
44 /* called before any console output */
45 int board_early_init_f(void)
47 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
48 volatile ccsr_gur_t *gur = &immap->im_gur;
50 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
59 /*Do not use 8259PIC*/
60 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
61 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val | 0x80);
63 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
64 version = in8(PIXIS_BASE + PIXIS_PVER);
66 tmp_val = in8(PIXIS_BASE + PIXIS_BRDCFG0);
67 out8(PIXIS_BASE + PIXIS_BRDCFG0, tmp_val & 0xbf);
70 /* Using this for DIU init before the driver in linux takes over
71 * Enable the TFP410 Encoder (I2C address 0x38)
75 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
76 /* Verify if enabled */
78 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
79 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
82 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
83 /* Verify if enabled */
85 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
86 debug("DVI Encoder Read: 0x%02lx\n",tmp_val);
88 #ifdef CONFIG_FSL_DIU_FB
89 mpc8610hpcd_diu_init();
97 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
98 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
100 printf ("Board: MPC8610HPCD, System ID: 0x%02x, "
101 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
102 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
103 in8(PIXIS_BASE + PIXIS_PVER));
105 mcm->abcr |= 0x00010000; /* 0 */
106 mcm->hpmr3 = 0x80000008; /* 4c */
118 initdram(int board_type)
120 phys_size_t dram_size = 0;
122 #if defined(CONFIG_SPD_EEPROM)
123 dram_size = fsl_ddr_sdram();
125 dram_size = fixed_sdram();
128 #if defined(CONFIG_SYS_RAMBOOT)
138 #if !defined(CONFIG_SPD_EEPROM)
140 * Fixed sdram init -- doesn't use serial presence detect.
143 phys_size_t fixed_sdram(void)
145 #if !defined(CONFIG_SYS_RAMBOOT)
146 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
147 volatile ccsr_ddr_t *ddr = &immap->im_ddr1;
150 ddr->cs0_bnds = 0x0000001f;
151 ddr->cs0_config = 0x80010202;
153 ddr->timing_cfg_3 = 0x00000000;
154 ddr->timing_cfg_0 = 0x00260802;
155 ddr->timing_cfg_1 = 0x3935d322;
156 ddr->timing_cfg_2 = 0x14904cc8;
157 ddr->sdram_mode_1 = 0x00480432;
158 ddr->sdram_mode_2 = 0x00000000;
159 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
160 ddr->sdram_data_init = 0xDEADBEEF;
161 ddr->sdram_clk_cntl = 0x03800000;
162 ddr->sdram_cfg_2 = 0x04400010;
164 #if defined(CONFIG_DDR_ECC)
165 ddr->err_int_en = 0x0000000d;
166 ddr->err_disable = 0x00000000;
167 ddr->err_sbe = 0x00010000;
173 ddr->sdram_cfg_1 = 0xc3000000; /* 0xe3008000;*/
176 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
178 debug("DDR - 1st controller: memory initializing\n");
180 * Poll until memory is initialized.
181 * 512 Meg at 400 might hit this 200 times or so.
183 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
186 debug("DDR: memory initialized\n\n");
191 return 512 * 1024 * 1024;
193 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
198 #if defined(CONFIG_PCI)
200 * Initialize PCI Devices, report devices found.
203 #ifndef CONFIG_PCI_PNP
204 static struct pci_config_table pci_fsl86xxads_config_table[] = {
205 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
206 PCI_IDSEL_NUMBER, PCI_ANY_ID,
207 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
209 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
215 static struct pci_controller pci1_hose = {
216 #ifndef CONFIG_PCI_PNP
217 config_table:pci_mpc86xxcts_config_table
220 #endif /* CONFIG_PCI */
223 static struct pci_controller pcie1_hose;
227 static struct pci_controller pcie2_hose;
230 int first_free_busno = 0;
232 void pci_init_board(void)
234 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
235 volatile ccsr_gur_t *gur = &immap->im_gur;
236 uint devdisr = gur->devdisr;
237 uint io_sel = (gur->pordevsr & MPC8610_PORDEVSR_IO_SEL)
238 >> MPC8610_PORDEVSR_IO_SEL_SHIFT;
239 uint host_agent = (gur->porbmsr & MPC8610_PORBMSR_HA)
240 >> MPC8610_PORBMSR_HA_SHIFT;
242 printf( " pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
243 devdisr, io_sel, host_agent);
247 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
248 struct pci_controller *hose = &pcie1_hose;
249 int pcie_configured = (io_sel == 1) || (io_sel == 4);
250 int pcie_ep = (host_agent == 0) || (host_agent == 2) ||
252 struct pci_region *r = hose->regions;
254 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE1)) {
255 printf(" PCIe 1 connected to Uli as %s (base address %x)\n",
256 pcie_ep ? "End Point" : "Root Complex",
258 if (pci->pme_msg_det)
259 pci->pme_msg_det = 0xffffffff;
262 r += fsl_pci_setup_inbound_windows(r);
264 /* outbound memory */
266 CONFIG_SYS_PCIE1_MEM_BUS,
267 CONFIG_SYS_PCIE1_MEM_PHYS,
268 CONFIG_SYS_PCIE1_MEM_SIZE,
273 CONFIG_SYS_PCIE1_IO_BUS,
274 CONFIG_SYS_PCIE1_IO_PHYS,
275 CONFIG_SYS_PCIE1_IO_SIZE,
278 hose->region_count = r - hose->regions;
280 hose->first_busno = first_free_busno;
281 pci_setup_indirect(hose, (int)&pci->cfg_addr,
282 (int)&pci->cfg_data);
286 first_free_busno = hose->last_busno + 1;
287 printf(" PCI-Express 1 on bus %02x - %02x\n",
288 hose->first_busno, hose->last_busno);
291 puts(" PCI-Express 1: Disabled\n");
294 puts("PCI-Express 1: Disabled\n");
295 #endif /* CONFIG_PCIE1 */
300 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
301 struct pci_controller *hose = &pcie2_hose;
302 struct pci_region *r = hose->regions;
304 int pcie_configured = (io_sel == 0) || (io_sel == 4);
305 int pcie_ep = (host_agent == 0) || (host_agent == 1) ||
308 if (pcie_configured && !(devdisr & MPC86xx_DEVDISR_PCIE2)) {
309 printf(" PCI-Express 2 connected to slot as %s" \
310 " (base address %x)\n",
311 pcie_ep ? "End Point" : "Root Complex",
313 if (pci->pme_msg_det)
314 pci->pme_msg_det = 0xffffffff;
317 r += fsl_pci_setup_inbound_windows(r);
319 /* outbound memory */
321 CONFIG_SYS_PCIE2_MEM_BUS,
322 CONFIG_SYS_PCIE2_MEM_PHYS,
323 CONFIG_SYS_PCIE2_MEM_SIZE,
328 CONFIG_SYS_PCIE2_IO_BUS,
329 CONFIG_SYS_PCIE2_IO_PHYS,
330 CONFIG_SYS_PCIE2_IO_SIZE,
333 hose->region_count = r - hose->regions;
335 hose->first_busno = first_free_busno;
336 pci_setup_indirect(hose, (int)&pci->cfg_addr,
337 (int)&pci->cfg_data);
341 first_free_busno = hose->last_busno + 1;
342 printf(" PCI-Express 2 on bus %02x - %02x\n",
343 hose->first_busno, hose->last_busno);
345 puts(" PCI-Express 2: Disabled\n");
348 puts("PCI-Express 2: Disabled\n");
349 #endif /* CONFIG_PCIE2 */
354 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
355 struct pci_controller *hose = &pci1_hose;
356 int pci_agent = (host_agent >= 4) && (host_agent <= 6);
357 struct pci_region *r = hose->regions;
359 if ( !(devdisr & MPC86xx_DEVDISR_PCI1)) {
360 printf(" PCI connected to PCI slots as %s" \
361 " (base address %x)\n",
362 pci_agent ? "Agent" : "Host",
366 r += fsl_pci_setup_inbound_windows(r);
368 /* outbound memory */
370 CONFIG_SYS_PCI1_MEM_BUS,
371 CONFIG_SYS_PCI1_MEM_PHYS,
372 CONFIG_SYS_PCI1_MEM_SIZE,
377 CONFIG_SYS_PCI1_IO_BUS,
378 CONFIG_SYS_PCI1_IO_PHYS,
379 CONFIG_SYS_PCI1_IO_SIZE,
382 hose->region_count = r - hose->regions;
384 hose->first_busno = first_free_busno;
385 pci_setup_indirect(hose, (int) &pci->cfg_addr,
386 (int) &pci->cfg_data);
390 first_free_busno = hose->last_busno + 1;
391 printf(" PCI on bus %02x - %02x\n",
392 hose->first_busno, hose->last_busno);
396 puts(" PCI: Disabled\n");
398 #endif /* CONFIG_PCI1 */
401 #if defined(CONFIG_OF_BOARD_SETUP)
403 ft_board_setup(void *blob, bd_t *bd)
405 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
406 "timebase-frequency", bd->bi_busfreq / 4, 1);
407 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
408 "bus-frequency", bd->bi_busfreq, 1);
409 do_fixup_by_prop_u32(blob, "device_type", "cpu", 4,
410 "clock-frequency", bd->bi_intfreq, 1);
411 do_fixup_by_prop_u32(blob, "device_type", "soc", 4,
412 "bus-frequency", bd->bi_busfreq, 1);
414 do_fixup_by_compat_u32(blob, "ns16550",
415 "clock-frequency", bd->bi_busfreq, 1);
417 fdt_fixup_memory(blob, bd->bi_memstart, bd->bi_memsize);
420 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
423 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
426 ft_fsl_pci_setup(blob, "pci2", &pcie2_hose);
433 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
437 get_board_sys_clk(ulong dummy)
443 a = PIXIS_BASE + PIXIS_SPD;
477 int board_eth_init(bd_t *bis)
479 return pci_eth_init(bis);
482 void board_reset(void)
484 out8(PIXIS_BASE + PIXIS_RST, 0);