2 * Copyright 2007,2009-2011 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/processor.h>
11 #include <asm/immap_86xx.h>
12 #include <asm/fsl_pci.h>
13 #include <fsl_ddr_sdram.h>
14 #include <asm/fsl_serdes.h>
18 #include <fdt_support.h>
19 #include <spd_sdram.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 void sdram_init(void);
25 phys_size_t fixed_sdram(void);
26 int mpc8610hpcd_diu_init(void);
29 /* called before any console output */
30 int board_early_init_f(void)
32 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
33 volatile ccsr_gur_t *gur = &immap->im_gur;
35 gur->gpiocr |= 0x88aa5500; /* DIU16, IR1, UART0, UART2 */
43 u8 *pixis_base = (u8 *)PIXIS_BASE;
45 /*Do not use 8259PIC*/
46 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
47 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val | 0x80);
49 /*For FPGA V7 or higher, set the IRQMAPSEL to 0 to use MAP0 interrupt*/
50 version = in_8(pixis_base + PIXIS_PVER);
52 tmp_val = in_8(pixis_base + PIXIS_BRDCFG0);
53 out_8(pixis_base + PIXIS_BRDCFG0, tmp_val & 0xbf);
56 /* Using this for DIU init before the driver in linux takes over
57 * Enable the TFP410 Encoder (I2C address 0x38)
61 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
62 /* Verify if enabled */
64 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
65 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
68 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
69 /* Verify if enabled */
71 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
72 debug("DVI Encoder Read: 0x%02x\n", tmp_val);
79 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
80 volatile ccsr_local_mcm_t *mcm = &immap->im_local_mcm;
81 u8 *pixis_base = (u8 *)PIXIS_BASE;
83 printf ("Board: MPC8610HPCD, Sys ID: 0x%02x, "
84 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
85 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
86 in_8(pixis_base + PIXIS_PVER));
89 * The MPC8610 HPCD workbook says that LBMAP=11 is the "normal" boot
90 * bank and LBMAP=00 is the alternate bank. However, the pixis
91 * altbank code can only set bits, not clear them, so we treat 00 as
92 * the normal bank and 11 as the alternate.
94 switch (in_8(pixis_base + PIXIS_VBOOT) & 0xC0) {
96 puts("vBank: Standard\n");
105 puts("vBank: Alternate\n");
109 mcm->abcr |= 0x00010000; /* 0 */
110 mcm->hpmr3 = 0x80000008; /* 4c */
123 phys_size_t dram_size = 0;
125 #if defined(CONFIG_SPD_EEPROM)
126 dram_size = fsl_ddr_sdram();
128 dram_size = fixed_sdram();
131 setup_ddr_bat(dram_size);
134 gd->ram_size = dram_size;
140 #if !defined(CONFIG_SPD_EEPROM)
142 * Fixed sdram init -- doesn't use serial presence detect.
145 phys_size_t fixed_sdram(void)
147 #if !defined(CONFIG_SYS_RAMBOOT)
148 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
149 struct ccsr_ddr __iomem *ddr = &immap->im_ddr1;
152 ddr->cs0_bnds = 0x0000001f;
153 ddr->cs0_config = 0x80010202;
155 ddr->timing_cfg_3 = 0x00000000;
156 ddr->timing_cfg_0 = 0x00260802;
157 ddr->timing_cfg_1 = 0x3935d322;
158 ddr->timing_cfg_2 = 0x14904cc8;
159 ddr->sdram_mode = 0x00480432;
160 ddr->sdram_mode_2 = 0x00000000;
161 ddr->sdram_interval = 0x06180fff; /* 0x06180100; */
162 ddr->sdram_data_init = 0xDEADBEEF;
163 ddr->sdram_clk_cntl = 0x03800000;
164 ddr->sdram_cfg_2 = 0x04400010;
166 #if defined(CONFIG_DDR_ECC)
167 ddr->err_int_en = 0x0000000d;
168 ddr->err_disable = 0x00000000;
169 ddr->err_sbe = 0x00010000;
175 ddr->sdram_cfg = 0xc3000000; /* 0xe3008000;*/
178 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
180 debug("DDR - 1st controller: memory initializing\n");
182 * Poll until memory is initialized.
183 * 512 Meg at 400 might hit this 200 times or so.
185 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0)
188 debug("DDR: memory initialized\n\n");
193 return 512 * 1024 * 1024;
195 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
200 #if defined(CONFIG_PCI)
202 * Initialize PCI Devices, report devices found.
205 #ifndef CONFIG_PCI_PNP
206 static struct pci_config_table pci_fsl86xxads_config_table[] = {
207 {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
208 PCI_IDSEL_NUMBER, PCI_ANY_ID,
209 pci_cfgfunc_config_device, {PCI_ENET0_IOADDR,
211 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER} },
217 static struct pci_controller pci1_hose;
218 #endif /* CONFIG_PCI */
220 void pci_init_board(void)
222 volatile immap_t *immap = (immap_t *) CONFIG_SYS_CCSRBAR;
223 volatile ccsr_gur_t *gur = &immap->im_gur;
224 struct fsl_pci_info pci_info;
226 int first_free_busno;
229 devdisr = in_be32(&gur->devdisr);
231 first_free_busno = fsl_pcie_init_board(0);
234 if (!(devdisr & MPC86xx_DEVDISR_PCI1)) {
235 SET_STD_PCI_INFO(pci_info, 1);
236 set_next_law(pci_info.mem_phys,
237 law_size_bits(pci_info.mem_size), pci_info.law);
238 set_next_law(pci_info.io_phys,
239 law_size_bits(pci_info.io_size), pci_info.law);
241 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
242 printf("PCI: connected to PCI slots as %s" \
243 " (base address %lx)\n",
244 pci_agent ? "Agent" : "Host",
246 #ifndef CONFIG_PCI_PNP
247 pci1_hose.config_table = pci_mpc86xxcts_config_table;
249 first_free_busno = fsl_pci_init_port(&pci_info,
250 &pci1_hose, first_free_busno);
252 printf("PCI: disabled\n");
257 setbits_be32(&gur->devdisr, MPC86xx_DEVDISR_PCI1); /* disable */
260 fsl_pcie_init_board(first_free_busno);
263 #if defined(CONFIG_OF_BOARD_SETUP)
264 int ft_board_setup(void *blob, bd_t *bd)
266 ft_cpu_setup(blob, bd);
276 * Reads the FPGA on board for CONFIG_SYS_CLK_FREQ
280 get_board_sys_clk(ulong dummy)
284 u8 *pixis_base = (u8 *)PIXIS_BASE;
286 i = in_8(pixis_base + PIXIS_SPD);
319 int board_eth_init(bd_t *bis)
321 return pci_eth_init(bis);
324 void board_reset(void)
326 u8 *pixis_base = (u8 *)PIXIS_BASE;
328 out_8(pixis_base + PIXIS_RST, 0);