board/freescale/mpc8572ds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008-2010 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/mmu.h>
  11
  12 struct fsl_e_tlb_entry tlb_table[] = {
  13         /* TLB 0 - for temp stack in cache */
  14         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  15                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                       0, 0, BOOKE_PAGESZ_4K, 0),
  26
  27         /* TLB 1 */
  28         /* *I*** - Covers boot page */
  29         SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  30                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  31                       0, 0, BOOKE_PAGESZ_4K, 1),
  32
  33         /* *I*G* - CCSRBAR */
  34         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  35                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  36                       0, 1, BOOKE_PAGESZ_1M, 1),
  37
  38         /* W**G* - Flash/promjet, localbus */
  39         /* This will be changed to *I*G* after relocation to RAM. */
  40         SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  41                       MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
  42                       0, 2, BOOKE_PAGESZ_256M, 1),
  43
  44 #ifndef CONFIG_NAND_SPL
  45         /* *I*G* - PCI */
  46         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  47                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  48                       0, 3, BOOKE_PAGESZ_1G, 1),
  49
  50         /* *I*G* - PCI */
  51         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  52                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  53                       0, 4, BOOKE_PAGESZ_256M, 1),
  54
  55         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000, CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  56                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  57                       0, 5, BOOKE_PAGESZ_256M, 1),
  58
  59         /* *I*G* - PCI I/O */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
  61                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62                       0, 6, BOOKE_PAGESZ_256K, 1),
  63 #endif
  64
  65         /* *I*G - NAND */
  66         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  67                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  68                       0, 7, BOOKE_PAGESZ_1M, 1),
  69
  70         SET_TLB_ENTRY(1, PIXIS_BASE, PIXIS_BASE_PHYS,
  71                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72                       0, 8, BOOKE_PAGESZ_4K, 1),
  73
  74 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  75         /* *I*G - L2SRAM */
  76         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR,
  77                         CONFIG_SYS_INIT_L2_ADDR_PHYS,
  78                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  79                         0, 9, BOOKE_PAGESZ_256K, 1),
  80         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  81                         CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  82                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  83                         0, 10, BOOKE_PAGESZ_256K, 1),
  84 #endif
  85 };
  86
  87 int num_tlb_entries = ARRAY_SIZE(tlb_table);