board/freescale/mpc8572ds/mpc8572ds.c

   1 /*
   2  * Copyright 2007-2008 Freescale Semiconductor, Inc.
   3  *
   4  * See file CREDITS for list of people who contributed to this
   5  * project.
   6  *
   7  * This program is free software; you can redistribute it and/or
   8  * modify it under the terms of the GNU General Public License as
   9  * published by the Free Software Foundation; either version 2 of
  10  * the License, or (at your option) any later version.
  11  *
  12  * This program is distributed in the hope that it will be useful,
  13  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  14  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15  * GNU General Public License for more details.
  16  *
  17  * You should have received a copy of the GNU General Public License
  18  * along with this program; if not, write to the Free Software
  19  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  20  * MA 02111-1307 USA
  21  */
  22
  23 #include <common.h>
  24 #include <command.h>
  25 #include <pci.h>
  26 #include <asm/processor.h>
  27 #include <asm/mmu.h>
  28 #include <asm/cache.h>
  29 #include <asm/immap_85xx.h>
  30 #include <asm/immap_fsl_pci.h>
  31 #include <asm/fsl_ddr_sdram.h>
  32 #include <asm/io.h>
  33 #include <miiphy.h>
  34 #include <libfdt.h>
  35 #include <fdt_support.h>
  36
  37 #include "../common/pixis.h"
  38
  39 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  40 extern void ddr_enable_ecc(unsigned int dram_size);
  41 #endif
  42
  43 long int fixed_sdram(void);
  44
  45 int checkboard (void)
  46 {
  47         printf ("Board: MPC8572DS, System ID: 0x%02x, "
  48                 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
  49                 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
  50                 in8(PIXIS_BASE + PIXIS_PVER));
  51         return 0;
  52 }
  53
  54 phys_size_t initdram(int board_type)
  55 {
  56         phys_size_t dram_size = 0;
  57
  58         puts("Initializing....");
  59
  60 #ifdef CONFIG_SPD_EEPROM
  61         dram_size = fsl_ddr_sdram();
  62
  63         dram_size = setup_ddr_tlbs(dram_size / 0x100000);
  64
  65         dram_size *= 0x100000;
  66 #else
  67         dram_size = fixed_sdram();
  68 #endif
  69
  70 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  71         /*
  72          * Initialize and enable DDR ECC.
  73          */
  74         ddr_enable_ecc(dram_size);
  75 #endif
  76         puts("    DDR: ");
  77         return dram_size;
  78 }
  79
  80 #if !defined(CONFIG_SPD_EEPROM)
  81 /*
  82  * Fixed sdram init -- doesn't use serial presence detect.
  83  */
  84
  85 phys_size_t fixed_sdram (void)
  86 {
  87         volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
  88         volatile ccsr_ddr_t *ddr= &immap->im_ddr;
  89         uint d_init;
  90
  91         ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
  92         ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
  93
  94         ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
  95         ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
  96         ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
  97         ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
  98         ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
  99         ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
 100         ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
 101         ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
 102         ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
 103         ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
 104
 105 #if defined (CONFIG_DDR_ECC)
 106         ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
 107         ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
 108         ddr->err_sbe = CONFIG_SYS_DDR_SBE;
 109 #endif
 110         asm("sync;isync");
 111
 112         udelay(500);
 113
 114         ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
 115
 116 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
 117         d_init = 1;
 118         debug("DDR - 1st controller: memory initializing\n");
 119         /*
 120          * Poll until memory is initialized.
 121          * 512 Meg at 400 might hit this 200 times or so.
 122          */
 123         while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
 124                 udelay(1000);
 125         }
 126         debug("DDR: memory initialized\n\n");
 127         asm("sync; isync");
 128         udelay(500);
 129 #endif
 130
 131         return 512 * 1024 * 1024;
 132 }
 133
 134 #endif
 135
 136 #ifdef CONFIG_PCIE1
 137 static struct pci_controller pcie1_hose;
 138 #endif
 139
 140 #ifdef CONFIG_PCIE2
 141 static struct pci_controller pcie2_hose;
 142 #endif
 143
 144 #ifdef CONFIG_PCIE3
 145 static struct pci_controller pcie3_hose;
 146 #endif
 147
 148 int first_free_busno=0;
 149 #ifdef CONFIG_PCI
 150 void pci_init_board(void)
 151 {
 152         volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
 153         uint devdisr = gur->devdisr;
 154         uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
 155         uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
 156
 157         debug ("   pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
 158                         devdisr, io_sel, host_agent);
 159
 160         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
 161                 printf ("    eTSEC1 is in sgmii mode.\n");
 162         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII2_DIS))
 163                 printf ("    eTSEC2 is in sgmii mode.\n");
 164         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
 165                 printf ("    eTSEC3 is in sgmii mode.\n");
 166         if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII4_DIS))
 167                 printf ("    eTSEC4 is in sgmii mode.\n");
 168
 169
 170 #ifdef CONFIG_PCIE3
 171         {
 172                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
 173                 extern void fsl_pci_init(struct pci_controller *hose);
 174                 struct pci_controller *hose = &pcie3_hose;
 175                 int pcie_ep = (host_agent == 0) || (host_agent == 3) ||
 176                         (host_agent == 5) || (host_agent == 6);
 177                 int pcie_configured  = io_sel >= 1;
 178                 u32 temp32;
 179
 180                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 181                         printf ("\n    PCIE3 connected to ULI as %s (base address %x)",
 182                                         pcie_ep ? "End Point" : "Root Complex",
 183                                         (uint)pci);
 184                         if (pci->pme_msg_det) {
 185                                 pci->pme_msg_det = 0xffffffff;
 186                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 187                         }
 188                         printf ("\n");
 189
 190                         /* inbound */
 191                         pci_set_region(hose->regions + 0,
 192                                         CONFIG_SYS_PCI_MEMORY_BUS,
 193                                         CONFIG_SYS_PCI_MEMORY_PHYS,
 194                                         CONFIG_SYS_PCI_MEMORY_SIZE,
 195                                         PCI_REGION_MEM | PCI_REGION_MEMORY);
 196
 197                         /* outbound memory */
 198                         pci_set_region(hose->regions + 1,
 199                                         CONFIG_SYS_PCIE3_MEM_BASE,
 200                                         CONFIG_SYS_PCIE3_MEM_PHYS,
 201                                         CONFIG_SYS_PCIE3_MEM_SIZE,
 202                                         PCI_REGION_MEM);
 203
 204                         /* outbound io */
 205                         pci_set_region(hose->regions + 2,
 206                                         CONFIG_SYS_PCIE3_IO_BASE,
 207                                         CONFIG_SYS_PCIE3_IO_PHYS,
 208                                         CONFIG_SYS_PCIE3_IO_SIZE,
 209                                         PCI_REGION_IO);
 210
 211                         hose->region_count = 3;
 212                         hose->first_busno=first_free_busno;
 213                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 214
 215                         fsl_pci_init(hose);
 216
 217                         first_free_busno=hose->last_busno+1;
 218                         printf ("    PCIE3 on bus %02x - %02x\n",
 219                                         hose->first_busno,hose->last_busno);
 220
 221                         /*
 222                          * Activate ULI1575 legacy chip by performing a fake
 223                          * memory access.  Needed to make ULI RTC work.
 224                          * Device 1d has the first on-board memory BAR.
 225                          */
 226
 227                         pci_hose_read_config_dword(hose, PCI_BDF(2, 0x1d, 0 ),
 228                                         PCI_BASE_ADDRESS_1, &temp32);
 229                         if (temp32 >= CONFIG_SYS_PCIE3_MEM_PHYS) {
 230                                 debug(" uli1572 read to %x\n", temp32);
 231                                 in_be32((unsigned *)temp32);
 232                         }
 233                 } else {
 234                         printf ("    PCIE3: disabled\n");
 235                 }
 236
 237         }
 238 #else
 239         gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
 240 #endif
 241
 242 #ifdef CONFIG_PCIE2
 243         {
 244                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
 245                 extern void fsl_pci_init(struct pci_controller *hose);
 246                 struct pci_controller *hose = &pcie2_hose;
 247                 int pcie_ep = (host_agent == 2) || (host_agent == 4) ||
 248                         (host_agent == 6) || (host_agent == 0);
 249                 int pcie_configured  = io_sel & 4;
 250
 251                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 252                         printf ("\n    PCIE2 connected to Slot 1 as %s (base address %x)",
 253                                         pcie_ep ? "End Point" : "Root Complex",
 254                                         (uint)pci);
 255                         if (pci->pme_msg_det) {
 256                                 pci->pme_msg_det = 0xffffffff;
 257                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 258                         }
 259                         printf ("\n");
 260
 261                         /* inbound */
 262                         pci_set_region(hose->regions + 0,
 263                                         CONFIG_SYS_PCI_MEMORY_BUS,
 264                                         CONFIG_SYS_PCI_MEMORY_PHYS,
 265                                         CONFIG_SYS_PCI_MEMORY_SIZE,
 266                                         PCI_REGION_MEM | PCI_REGION_MEMORY);
 267
 268                         /* outbound memory */
 269                         pci_set_region(hose->regions + 1,
 270                                         CONFIG_SYS_PCIE2_MEM_BASE,
 271                                         CONFIG_SYS_PCIE2_MEM_PHYS,
 272                                         CONFIG_SYS_PCIE2_MEM_SIZE,
 273                                         PCI_REGION_MEM);
 274
 275                         /* outbound io */
 276                         pci_set_region(hose->regions + 2,
 277                                         CONFIG_SYS_PCIE2_IO_BASE,
 278                                         CONFIG_SYS_PCIE2_IO_PHYS,
 279                                         CONFIG_SYS_PCIE2_IO_SIZE,
 280                                         PCI_REGION_IO);
 281
 282                         hose->region_count = 3;
 283                         hose->first_busno=first_free_busno;
 284                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 285
 286                         fsl_pci_init(hose);
 287                         first_free_busno=hose->last_busno+1;
 288                         printf ("    PCIE2 on bus %02x - %02x\n",
 289                                         hose->first_busno,hose->last_busno);
 290
 291                 } else {
 292                         printf ("    PCIE2: disabled\n");
 293                 }
 294
 295         }
 296 #else
 297         gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
 298 #endif
 299 #ifdef CONFIG_PCIE1
 300         {
 301                 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
 302                 extern void fsl_pci_init(struct pci_controller *hose);
 303                 struct pci_controller *hose = &pcie1_hose;
 304                 int pcie_ep = (host_agent <= 1) || (host_agent == 4) ||
 305                         (host_agent == 5);
 306                 int pcie_configured  = io_sel & 6;
 307
 308                 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
 309                         printf ("\n    PCIE1 connected to Slot 2 as %s (base address %x)",
 310                                         pcie_ep ? "End Point" : "Root Complex",
 311                                         (uint)pci);
 312                         if (pci->pme_msg_det) {
 313                                 pci->pme_msg_det = 0xffffffff;
 314                                 debug (" with errors.  Clearing.  Now 0x%08x",pci->pme_msg_det);
 315                         }
 316                         printf ("\n");
 317
 318                         /* inbound */
 319                         pci_set_region(hose->regions + 0,
 320                                         CONFIG_SYS_PCI_MEMORY_BUS,
 321                                         CONFIG_SYS_PCI_MEMORY_PHYS,
 322                                         CONFIG_SYS_PCI_MEMORY_SIZE,
 323                                         PCI_REGION_MEM | PCI_REGION_MEMORY);
 324
 325                         /* outbound memory */
 326                         pci_set_region(hose->regions + 1,
 327                                         CONFIG_SYS_PCIE1_MEM_BASE,
 328                                         CONFIG_SYS_PCIE1_MEM_PHYS,
 329                                         CONFIG_SYS_PCIE1_MEM_SIZE,
 330                                         PCI_REGION_MEM);
 331
 332                         /* outbound io */
 333                         pci_set_region(hose->regions + 2,
 334                                         CONFIG_SYS_PCIE1_IO_BASE,
 335                                         CONFIG_SYS_PCIE1_IO_PHYS,
 336                                         CONFIG_SYS_PCIE1_IO_SIZE,
 337                                         PCI_REGION_IO);
 338
 339                         hose->region_count = 3;
 340                         hose->first_busno=first_free_busno;
 341
 342                         pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
 343
 344                         fsl_pci_init(hose);
 345
 346                         first_free_busno=hose->last_busno+1;
 347                         printf("    PCIE1 on bus %02x - %02x\n",
 348                                         hose->first_busno,hose->last_busno);
 349
 350                 } else {
 351                         printf ("    PCIE1: disabled\n");
 352                 }
 353
 354         }
 355 #else
 356         gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
 357 #endif
 358 }
 359 #endif
 360
 361 int board_early_init_r(void)
 362 {
 363         const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
 364         const u8 flash_esel = 2;
 365
 366         /*
 367          * Remap Boot flash + PROMJET region to caching-inhibited
 368          * so that flash can be erased properly.
 369          */
 370
 371         /* Flush d-cache and invalidate i-cache of any FLASH data */
 372         flush_dcache();
 373         invalidate_icache();
 374
 375         /* invalidate existing TLB entry for flash + promjet */
 376         disable_tlb(flash_esel);
 377
 378         set_tlb(1, flashbase, flashbase,                /* tlb, epn, rpn */
 379                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
 380                         0, flash_esel, BOOKE_PAGESZ_256M, 1);   /* ts, esel, tsize, iprot */
 381
 382         return 0;
 383 }
 384
 385 #ifdef CONFIG_GET_CLK_FROM_ICS307
 386 /* decode S[0-2] to Output Divider (OD) */
 387 static unsigned char ics307_S_to_OD[] = {
 388         10, 2, 8, 4, 5, 7, 3, 6
 389 };
 390
 391 /* Calculate frequency being generated by ICS307-02 clock chip based upon
 392  * the control bytes being programmed into it. */
 393 /* XXX: This function should probably go into a common library */
 394 static unsigned long
 395 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
 396 {
 397         const unsigned long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
 398         unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
 399         unsigned long RDW = cw2 & 0x7F;
 400         unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
 401         unsigned long freq;
 402
 403         /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
 404
 405         /* cw0:  C1 C0 TTL F1 F0 S2 S1 S0
 406          * cw1:  V8 V7 V6 V5 V4 V3 V2 V1
 407          * cw2:  V0 R6 R5 R4 R3 R2 R1 R0
 408          *
 409          * R6:R0 = Reference Divider Word (RDW)
 410          * V8:V0 = VCO Divider Word (VDW)
 411          * S2:S0 = Output Divider Select (OD)
 412          * F1:F0 = Function of CLK2 Output
 413          * TTL = duty cycle
 414          * C1:C0 = internal load capacitance for cyrstal
 415          */
 416
 417         /* Adding 1 to get a "nicely" rounded number, but this needs
 418          * more tweaking to get a "properly" rounded number. */
 419
 420         freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
 421
 422         debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
 423                         freq);
 424         return freq;
 425 }
 426
 427 unsigned long get_board_sys_clk(ulong dummy)
 428 {
 429         return ics307_clk_freq (
 430                         in8(PIXIS_BASE + PIXIS_VSYSCLK0),
 431                         in8(PIXIS_BASE + PIXIS_VSYSCLK1),
 432                         in8(PIXIS_BASE + PIXIS_VSYSCLK2)
 433                         );
 434 }
 435
 436 unsigned long get_board_ddr_clk(ulong dummy)
 437 {
 438         return ics307_clk_freq (
 439                         in8(PIXIS_BASE + PIXIS_VDDRCLK0),
 440                         in8(PIXIS_BASE + PIXIS_VDDRCLK1),
 441                         in8(PIXIS_BASE + PIXIS_VDDRCLK2)
 442                         );
 443 }
 444 #else
 445 unsigned long get_board_sys_clk(ulong dummy)
 446 {
 447         u8 i;
 448         ulong val = 0;
 449
 450         i = in8(PIXIS_BASE + PIXIS_SPD);
 451         i &= 0x07;
 452
 453         switch (i) {
 454                 case 0:
 455                         val = 33333333;
 456                         break;
 457                 case 1:
 458                         val = 40000000;
 459                         break;
 460                 case 2:
 461                         val = 50000000;
 462                         break;
 463                 case 3:
 464                         val = 66666666;
 465                         break;
 466                 case 4:
 467                         val = 83333333;
 468                         break;
 469                 case 5:
 470                         val = 100000000;
 471                         break;
 472                 case 6:
 473                         val = 133333333;
 474                         break;
 475                 case 7:
 476                         val = 166666666;
 477                         break;
 478         }
 479
 480         return val;
 481 }
 482
 483 unsigned long get_board_ddr_clk(ulong dummy)
 484 {
 485         u8 i;
 486         ulong val = 0;
 487
 488         i = in8(PIXIS_BASE + PIXIS_SPD);
 489         i &= 0x38;
 490         i >>= 3;
 491
 492         switch (i) {
 493                 case 0:
 494                         val = 33333333;
 495                         break;
 496                 case 1:
 497                         val = 40000000;
 498                         break;
 499                 case 2:
 500                         val = 50000000;
 501                         break;
 502                 case 3:
 503                         val = 66666666;
 504                         break;
 505                 case 4:
 506                         val = 83333333;
 507                         break;
 508                 case 5:
 509                         val = 100000000;
 510                         break;
 511                 case 6:
 512                         val = 133333333;
 513                         break;
 514                 case 7:
 515                         val = 166666666;
 516                         break;
 517         }
 518         return val;
 519 }
 520 #endif
 521
 522 #if defined(CONFIG_OF_BOARD_SETUP)
 523 void ft_board_setup(void *blob, bd_t *bd)
 524 {
 525         int node, tmp[2];
 526         const char *path;
 527         ulong base, size;
 528
 529         ft_cpu_setup(blob, bd);
 530
 531         base = getenv_bootm_low();
 532         size = getenv_bootm_size();
 533
 534         fdt_fixup_memory(blob, (u64)base, (u64)size);
 535
 536         node = fdt_path_offset(blob, "/aliases");
 537         tmp[0] = 0;
 538         if (node >= 0) {
 539 #ifdef CONFIG_PCIE3
 540                 path = fdt_getprop(blob, node, "pci0", NULL);
 541                 if (path) {
 542                         tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
 543                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 544                 }
 545 #endif
 546 #ifdef CONFIG_PCIE2
 547                 path = fdt_getprop(blob, node, "pci1", NULL);
 548                 if (path) {
 549                         tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
 550                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 551                 }
 552 #endif
 553 #ifdef CONFIG_PCIE1
 554                 path = fdt_getprop(blob, node, "pci2", NULL);
 555                 if (path) {
 556                         tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
 557                         do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
 558                 }
 559 #endif
 560         }
 561 }
 562 #endif
 563
 564 #ifdef CONFIG_MP
 565 extern void cpu_mp_lmb_reserve(struct lmb *lmb);
 566
 567 void board_lmb_reserve(struct lmb *lmb)
 568 {
 569         cpu_mp_lmb_reserve(lmb);
 570 }
 571 #endif