2 * Copyright 2007-2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
36 #include <fdt_support.h>
41 #include "../common/sgmii_riser.h"
46 u8 *pixis_base = (u8 *)PIXIS_BASE;
48 printf("Board: MPC8572DS Sys ID: 0x%02x, "
49 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
50 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
51 in_8(pixis_base + PIXIS_PVER));
53 vboot = in_8(pixis_base + PIXIS_VBOOT);
54 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 6) {
55 case PIXIS_VBOOT_LBMAP_NOR0:
58 case PIXIS_VBOOT_LBMAP_PJET:
61 case PIXIS_VBOOT_LBMAP_NAND:
64 case PIXIS_VBOOT_LBMAP_NOR1:
73 #if !defined(CONFIG_SPD_EEPROM)
75 * Fixed sdram init -- doesn't use serial presence detect.
78 phys_size_t fixed_sdram (void)
80 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
81 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
84 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
85 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
87 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
88 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
89 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
90 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
91 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
92 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
93 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
94 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
95 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
96 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
98 #if defined (CONFIG_DDR_ECC)
99 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
100 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
101 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
107 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
109 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
111 debug("DDR - 1st controller: memory initializing\n");
113 * Poll until memory is initialized.
114 * 512 Meg at 400 might hit this 200 times or so.
116 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
119 debug("DDR: memory initialized\n\n");
124 return 512 * 1024 * 1024;
130 void pci_init_board(void)
132 struct pci_controller *hose;
134 fsl_pcie_init_board(0);
136 hose = find_hose_by_cfg_addr((void *)(CONFIG_SYS_PCIE3_ADDR));
140 u8 uli_busno = hose->first_busno + 2;
143 * Activate ULI1575 legacy chip by performing a fake
144 * memory access. Needed to make ULI RTC work.
145 * Device 1d has the first on-board memory BAR.
147 pci_hose_read_config_dword(hose, PCI_BDF(uli_busno, 0x1d, 0),
148 PCI_BASE_ADDRESS_1, &temp32);
150 if (temp32 >= CONFIG_SYS_PCIE3_MEM_BUS) {
151 void *p = pci_mem_to_virt(PCI_BDF(uli_busno, 0x1d, 0),
153 debug(" uli1572 read to %p\n", p);
160 int board_early_init_r(void)
162 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
163 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
166 * Remap Boot flash + PROMJET region to caching-inhibited
167 * so that flash can be erased properly.
170 /* Flush d-cache and invalidate i-cache of any FLASH data */
174 /* invalidate existing TLB entry for flash + promjet */
175 disable_tlb(flash_esel);
177 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
178 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
179 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
184 #ifdef CONFIG_TSEC_ENET
185 int board_eth_init(bd_t *bis)
187 struct fsl_pq_mdio_info mdio_info;
188 struct tsec_info_struct tsec_info[4];
192 SET_STD_TSEC_INFO(tsec_info[num], 1);
193 if (is_serdes_configured(SGMII_TSEC1)) {
194 puts("eTSEC1 is in sgmii mode.\n");
195 tsec_info[num].flags |= TSEC_SGMII;
200 SET_STD_TSEC_INFO(tsec_info[num], 2);
201 if (is_serdes_configured(SGMII_TSEC2)) {
202 puts("eTSEC2 is in sgmii mode.\n");
203 tsec_info[num].flags |= TSEC_SGMII;
208 SET_STD_TSEC_INFO(tsec_info[num], 3);
209 if (is_serdes_configured(SGMII_TSEC3)) {
210 puts("eTSEC3 is in sgmii mode.\n");
211 tsec_info[num].flags |= TSEC_SGMII;
216 SET_STD_TSEC_INFO(tsec_info[num], 4);
217 if (is_serdes_configured(SGMII_TSEC4)) {
218 puts("eTSEC4 is in sgmii mode.\n");
219 tsec_info[num].flags |= TSEC_SGMII;
225 printf("No TSECs initialized\n");
230 #ifdef CONFIG_FSL_SGMII_RISER
231 fsl_sgmii_riser_init(tsec_info, num);
234 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
235 mdio_info.name = DEFAULT_MII_NAME;
236 fsl_pq_mdio_init(bis, &mdio_info);
238 tsec_eth_init(bis, tsec_info, num);
240 return pci_eth_init(bis);
244 #if defined(CONFIG_OF_BOARD_SETUP)
245 void ft_board_setup(void *blob, bd_t *bd)
250 ft_cpu_setup(blob, bd);
252 base = getenv_bootm_low();
253 size = getenv_bootm_size();
255 fdt_fixup_memory(blob, (u64)base, (u64)size);
259 #ifdef CONFIG_FSL_SGMII_RISER
260 fsl_sgmii_riser_fdt_fixup(blob);