1 // SPDX-License-Identifier: GPL-2.0
3 * Copyright 2008 Freescale Semiconductor, Inc.
8 #include <fsl_ddr_sdram.h>
9 #include <fsl_ddr_dimm_params.h>
11 struct board_specific_parameters {
13 u32 datarate_mhz_high;
21 * This table contains all valid speeds we want to override with board
22 * specific parameters. datarate_mhz_high values need to be in ascending order
23 * for each n_ranks group.
25 * For DDR2 DIMM, all combinations of clk_adjust and write_data_delay have been
26 * tested. For RDIMM, clk_adjust = 4 and write_data_delay = 3 is optimized for
27 * all clocks from 400MT/s to 800MT/s, verified with Kingston KVR800D2D8P6/2G.
28 * For UDIMM, clk_adjust = 8 and write_delay = 5 is optimized for all clocks
29 * from 400MT/s to 800MT/s, verified with Micron MT18HTF25672AY-800E1.
31 * CPO value doesn't matter if workaround for errata 111 and 134 enabled.
33 static const struct board_specific_parameters udimm0[] = {
36 * num| hi| clk| cpo|wrdata|2T
37 * ranks| mhz|adjst| | delay|
41 {2, 549, 8, 11, 5, 0},
42 {2, 680, 8, 10, 5, 0},
43 {2, 850, 8, 12, 5, 1},
46 {1, 549, 6, 11, 3, 0},
47 {1, 680, 1, 10, 5, 0},
48 {1, 850, 1, 12, 5, 0},
52 static const struct board_specific_parameters udimm1[] = {
55 * num| hi| clk| cpo|wrdata|2T
56 * ranks| mhz|adjst| | delay|
60 {2, 549, 8, 11, 5, 0},
61 {2, 680, 8, 11, 5, 0},
62 {2, 850, 8, 13, 5, 1},
65 {1, 549, 6, 11, 3, 0},
66 {1, 680, 1, 11, 6, 0},
67 {1, 850, 1, 13, 6, 0},
71 static const struct board_specific_parameters *udimms[] = {
76 static const struct board_specific_parameters rdimm0[] = {
79 * num| hi| clk| cpo|wrdata|2T
80 * ranks| mhz|adjst| | delay|
84 {2, 549, 4, 11, 3, 0},
85 {2, 680, 4, 10, 3, 0},
86 {2, 850, 4, 12, 3, 1},
90 static const struct board_specific_parameters rdimm1[] = {
93 * num| hi| clk| cpo|wrdata|2T
94 * ranks| mhz|adjst| | delay|
98 {2, 549, 4, 11, 3, 0},
99 {2, 680, 4, 11, 3, 0},
100 {2, 850, 4, 13, 3, 1},
104 static const struct board_specific_parameters *rdimms[] = {
109 void fsl_ddr_board_options(memctl_options_t *popts,
110 dimm_params_t *pdimm,
111 unsigned int ctrl_num)
113 const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
117 printf("Wrong parameter for controller number %d", ctrl_num);
123 if (popts->registered_dimm_en)
124 pbsp = rdimms[ctrl_num];
126 pbsp = udimms[ctrl_num];
128 /* Get clk_adjust, cpo, write_data_delay,2T, according to the board ddr
129 * freqency and n_banks specified in board_specific_parameters table.
131 ddr_freq = get_ddr_freq(0) / 1000000;
132 while (pbsp->datarate_mhz_high) {
133 if (pbsp->n_ranks == pdimm->n_ranks) {
134 if (ddr_freq <= pbsp->datarate_mhz_high) {
135 popts->clk_adjust = pbsp->clk_adjust;
136 popts->cpo_override = pbsp->cpo;
137 popts->write_data_delay =
138 pbsp->write_data_delay;
139 popts->twot_en = pbsp->force_2t;
148 printf("Error: board specific timing not found "
149 "for data rate %lu MT/s!\n"
150 "Trying to use the highest speed (%u) parameters\n",
151 ddr_freq, pbsp_highest->datarate_mhz_high);
152 popts->clk_adjust = pbsp->clk_adjust;
153 popts->cpo_override = pbsp->cpo;
154 popts->write_data_delay = pbsp->write_data_delay;
155 popts->twot_en = pbsp->force_2t;
157 panic("DIMM is not supported by this board");
162 * Factors to consider for half-strength driver enable:
163 * - number of DIMMs installed
165 popts->half_strength_driver_enable = 0;