board/freescale/mpc8569mds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2009-2010 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/mmu.h>
  11
  12 struct fsl_e_tlb_entry tlb_table[] = {
  13         /* TLB 0 - for temp stack in cache */
  14         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  15                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  19                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  20                       0, 0, BOOKE_PAGESZ_4K, 0),
  21         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  22                       CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  23                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  24                       0, 0, BOOKE_PAGESZ_4K, 0),
  25         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  26                       CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  27                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  28                       0, 0, BOOKE_PAGESZ_4K, 0),
  29
  30         /* TLB 1 Initializations */
  31         /*
  32          * TLBe 0:      64M     write-through, guarded
  33          * Out of reset this entry is only 4K.
  34          * 0xfc000000   32MB    NAND FLASH (CS3)
  35          * 0xfe000000   32MB    NOR FLASH (CS0)
  36          */
  37 #ifdef CONFIG_NAND_SPL
  38         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
  39                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  40                       0, 0, BOOKE_PAGESZ_1M, 1),
  41 #else
  42         SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE,
  43                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  44                       0, 0, BOOKE_PAGESZ_64M, 1),
  45 #endif
  46         /*
  47          * TLBe 1:      256KB   Non-cacheable, guarded
  48          * 0xf8000000   32K     BCSR
  49          * 0xf8008000   32K     PIB (CS4)
  50          * 0xf8010000   32K     PIB (CS5)
  51          */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_BCSR_BASE, CONFIG_SYS_BCSR_BASE_PHYS,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 1, BOOKE_PAGESZ_256K, 1),
  55
  56         /*
  57          * TLBe 2:      256M    Non-cacheable, guarded
  58          * 0xa00000000  256M    PCIe MEM (lower half)
  59          */
  60         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS,
  61                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62                       0, 2, BOOKE_PAGESZ_256M, 1),
  63
  64         /*
  65          * TLBe 3:      256M    Non-cacheable, guarded
  66          * 0xb00000000  256M    PCIe MEM (higher half)
  67          */
  68         SET_TLB_ENTRY(1, (CONFIG_SYS_PCIE1_MEM_VIRT + 0x10000000),
  69                       (CONFIG_SYS_PCIE1_MEM_PHYS + 0x10000000),
  70                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 3, BOOKE_PAGESZ_256M, 1),
  72
  73         /*
  74          * TLBe 4:      64M     Non-cacheable, guarded
  75          * 0xe000_0000  1M      CCSRBAR
  76          * 0xe280_0000  8M      PCIe IO
  77          */
  78         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  79                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  80                       0, 4, BOOKE_PAGESZ_64M, 1),
  81
  82 #if defined(CONFIG_SYS_RAMBOOT) && defined(CONFIG_SYS_INIT_L2_ADDR)
  83         /* *I*G - L2SRAM */
  84         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR, CONFIG_SYS_INIT_L2_ADDR_PHYS,
  85                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  86                         0, 5, BOOKE_PAGESZ_256K, 1),
  87         SET_TLB_ENTRY(1, CONFIG_SYS_INIT_L2_ADDR + 0x40000,
  88                         CONFIG_SYS_INIT_L2_ADDR_PHYS + 0x40000,
  89                         MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  90                         0, 6, BOOKE_PAGESZ_256K, 1),
  91 #endif
  92 };
  93
  94 int num_tlb_entries = ARRAY_SIZE(tlb_table);