2 * Copyright 2009 Freescale Semiconductor.
4 * (C) Copyright 2002 Scott McNutt <smcnutt@artesyncp.com>
6 * See file CREDITS for list of people who contributed to this
9 * This program is free software; you can redistribute it and/or
10 * modify it under the terms of the GNU General Public License as
11 * published by the Free Software Foundation; either version 2 of
12 * the License, or (at your option) any later version.
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/processor.h>
30 #include <asm/immap_85xx.h>
31 #include <asm/fsl_pci.h>
32 #include <asm/fsl_ddr_sdram.h>
34 #include <spd_sdram.h>
38 #include <fdt_support.h>
39 #include <fsl_esdhc.h>
43 phys_size_t fixed_sdram(void);
45 const qe_iop_conf_t qe_iop_conf_tab[] = {
47 {2, 31, 1, 0, 1}, /* QE_MUX_MDC */
50 {2, 30, 3, 0, 2}, /* QE_MUX_MDIO */
52 #if defined(CONFIG_SYS_UCC_RGMII_MODE)
54 {2, 11, 2, 0, 1}, /* CLK12 */
55 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
56 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
57 {0, 2, 1, 0, 1}, /* ENET1_TXD2_SER1_TXD2 */
58 {0, 3, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
59 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
60 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
61 {0, 8, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
62 {0, 9, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
63 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
64 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
65 {2, 8, 2, 0, 1}, /* ENET1_GRXCLK */
66 {2, 20, 1, 0, 2}, /* ENET1_GTXCLK */
69 {2, 16, 2, 0, 3}, /* CLK17 */
70 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
71 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
72 {0, 16, 1, 0, 1}, /* ENET2_TXD2_SER2_TXD2 */
73 {0, 17, 1, 0, 1}, /* ENET2_TXD3_SER2_TXD3 */
74 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
75 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
76 {0, 22, 2, 0, 1}, /* ENET2_RXD2_SER2_RXD2 */
77 {0, 23, 2, 0, 1}, /* ENET2_RXD3_SER2_RXD3 */
78 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
79 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
80 {2, 3, 2, 0, 1}, /* ENET2_GRXCLK */
81 {2, 2, 1, 0, 2}, /* ENET2_GTXCLK */
84 {2, 11, 2, 0, 1}, /* CLK12 */
85 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
86 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
87 {0, 31, 1, 0, 2}, /* ENET3_TXD2_SER3_TXD2 */
88 {1, 0, 1, 0, 3}, /* ENET3_TXD3_SER3_TXD3 */
89 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
90 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
91 {1, 5, 2, 0, 2}, /* ENET3_RXD2_SER3_RXD2 */
92 {1, 6, 2, 0, 3}, /* ENET3_RXD3_SER3_RXD3 */
93 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
94 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
95 {2, 9, 2, 0, 2}, /* ENET3_GRXCLK */
96 {2, 25, 1, 0, 2}, /* ENET3_GTXCLK */
99 {2, 16, 2, 0, 3}, /* CLK17 */
100 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
101 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
102 {1, 14, 1, 0, 1}, /* ENET4_TXD2_SER4_TXD2 */
103 {1, 15, 1, 0, 2}, /* ENET4_TXD3_SER4_TXD3 */
104 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
105 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
106 {1, 20, 2, 0, 1}, /* ENET4_RXD2_SER4_RXD2 */
107 {1, 21, 2, 0, 2}, /* ENET4_RXD3_SER4_RXD3 */
108 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
109 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
110 {2, 17, 2, 0, 2}, /* ENET4_GRXCLK */
111 {2, 24, 1, 0, 2}, /* ENET4_GTXCLK */
113 #elif defined(CONFIG_SYS_UCC_RMII_MODE)
115 {2, 15, 2, 0, 1}, /* CLK16 */
116 {0, 0, 1, 0, 3}, /* ENET1_TXD0_SER1_TXD0 */
117 {0, 1, 1, 0, 3}, /* ENET1_TXD1_SER1_TXD1 */
118 {0, 6, 2, 0, 3}, /* ENET1_RXD0_SER1_RXD0 */
119 {0, 7, 2, 0, 1}, /* ENET1_RXD1_SER1_RXD1 */
120 {0, 4, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
121 {0, 12, 2, 0, 3}, /* ENET1_RX_DV_SER1_CTS_B */
124 {2, 15, 2, 0, 1}, /* CLK16 */
125 {0, 14, 1, 0, 2}, /* ENET2_TXD0_SER2_TXD0 */
126 {0, 15, 1, 0, 2}, /* ENET2_TXD1_SER2_TXD1 */
127 {0, 20, 2, 0, 2}, /* ENET2_RXD0_SER2_RXD0 */
128 {0, 21, 2, 0, 1}, /* ENET2_RXD1_SER2_RXD1 */
129 {0, 18, 1, 0, 2}, /* ENET2_TX_EN_SER2_RTS_B */
130 {0, 26, 2, 0, 3}, /* ENET2_RX_DV_SER2_CTS_B */
133 {2, 15, 2, 0, 1}, /* CLK16 */
134 {0, 29, 1, 0, 2}, /* ENET3_TXD0_SER3_TXD0 */
135 {0, 30, 1, 0, 3}, /* ENET3_TXD1_SER3_TXD1 */
136 {1, 3, 2, 0, 3}, /* ENET3_RXD0_SER3_RXD0 */
137 {1, 4, 2, 0, 1}, /* ENET3_RXD1_SER3_RXD1 */
138 {1, 1, 1, 0, 1}, /* ENET3_TX_EN_SER3_RTS_B */
139 {1, 9, 2, 0, 3}, /* ENET3_RX_DV_SER3_CTS_B */
142 {2, 15, 2, 0, 1}, /* CLK16 */
143 {1, 12, 1, 0, 2}, /* ENET4_TXD0_SER4_TXD0 */
144 {1, 13, 1, 0, 2}, /* ENET4_TXD1_SER4_TXD1 */
145 {1, 18, 2, 0, 2}, /* ENET4_RXD0_SER4_RXD0 */
146 {1, 19, 2, 0, 1}, /* ENET4_RXD1_SER4_RXD1 */
147 {1, 16, 1, 0, 2}, /* ENET4_TX_EN_SER4_RTS_B */
148 {1, 24, 2, 0, 3}, /* ENET4_RX_DV_SER4_CTS_B */
151 /* UART1 is muxed with QE PortF bit [9-12].*/
152 {5, 12, 2, 0, 3}, /* UART1_SIN */
153 {5, 9, 1, 0, 3}, /* UART1_SOUT */
154 {5, 10, 2, 0, 3}, /* UART1_CTS_B */
155 {5, 11, 1, 0, 2}, /* UART1_RTS_B */
158 {0, 19, 1, 0, 2}, /* QEUART_TX */
159 {1, 17, 2, 0, 3}, /* QEUART_RX */
160 {0, 25, 1, 0, 1}, /* QEUART_RTS */
161 {1, 23, 2, 0, 1}, /* QEUART_CTS */
163 /* SPI Flash, M25P40 */
164 {4, 27, 3, 0, 1}, /* SPI_MOSI */
165 {4, 28, 3, 0, 1}, /* SPI_MISO */
166 {4, 29, 3, 0, 1}, /* SPI_CLK */
167 {4, 30, 1, 0, 0}, /* SPI_SEL, GPIO */
169 {0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
172 void local_bus_init(void);
174 int board_early_init_f (void)
177 * Initialize local bus.
181 enable_8569mds_flash_write();
184 enable_8569mds_qe_uec();
187 #if CONFIG_SYS_I2C2_OFFSET
188 /* Enable I2C2 signals instead of SD signals */
189 volatile struct ccsr_gur *gur;
190 gur = (struct ccsr_gur *)(CONFIG_SYS_IMMR + 0xe0000);
191 gur->plppar1 &= ~PLPPAR1_I2C_BIT_MASK;
192 gur->plppar1 |= PLPPAR1_I2C2_VAL;
193 gur->plpdir1 &= ~PLPDIR1_I2C_BIT_MASK;
194 gur->plpdir1 |= PLPDIR1_I2C2_VAL;
196 disable_8569mds_brd_eeprom_write_protect();
202 int checkboard (void)
204 printf ("Board: 8569 MDS\n");
210 initdram(int board_type)
214 puts("Initializing\n");
216 #if defined(CONFIG_DDR_DLL)
218 * Work around to stabilize DDR DLL MSYNC_IN.
219 * Errata DDR9 seems to have been fixed.
220 * This is now the workaround for Errata DDR11:
221 * Override DLL = 1, Course Adj = 1, Tap Select = 0
223 volatile ccsr_gur_t *gur =
224 (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
226 out_be32(&gur->ddrdllcr, 0x81000000);
230 #ifdef CONFIG_SPD_EEPROM
231 dram_size = fsl_ddr_sdram();
233 dram_size = fixed_sdram();
236 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
237 dram_size *= 0x100000;
243 #if !defined(CONFIG_SPD_EEPROM)
244 phys_size_t fixed_sdram(void)
246 volatile ccsr_ddr_t *ddr = (ccsr_ddr_t *)CONFIG_SYS_MPC85xx_DDR_ADDR;
249 out_be32(&ddr->cs0_bnds, CONFIG_SYS_DDR_CS0_BNDS);
250 out_be32(&ddr->cs0_config, CONFIG_SYS_DDR_CS0_CONFIG);
251 out_be32(&ddr->timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
252 out_be32(&ddr->timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
253 out_be32(&ddr->timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
254 out_be32(&ddr->timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
255 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
256 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
257 out_be32(&ddr->sdram_mode, CONFIG_SYS_DDR_SDRAM_MODE);
258 out_be32(&ddr->sdram_mode_2, CONFIG_SYS_DDR_SDRAM_MODE_2);
259 out_be32(&ddr->sdram_interval, CONFIG_SYS_DDR_SDRAM_INTERVAL);
260 out_be32(&ddr->sdram_data_init, CONFIG_SYS_DDR_DATA_INIT);
261 out_be32(&ddr->sdram_clk_cntl, CONFIG_SYS_DDR_SDRAM_CLK_CNTL);
262 out_be32(&ddr->timing_cfg_4, CONFIG_SYS_DDR_TIMING_4);
263 out_be32(&ddr->timing_cfg_5, CONFIG_SYS_DDR_TIMING_5);
264 out_be32(&ddr->ddr_zq_cntl, CONFIG_SYS_DDR_ZQ_CNTL);
265 out_be32(&ddr->ddr_wrlvl_cntl, CONFIG_SYS_DDR_WRLVL_CNTL);
266 out_be32(&ddr->sdram_cfg_2, CONFIG_SYS_DDR_SDRAM_CFG_2);
267 #if defined (CONFIG_DDR_ECC)
268 out_be32(&ddr->err_int_en, CONFIG_SYS_DDR_ERR_INT_EN);
269 out_be32(&ddr->err_disable, CONFIG_SYS_DDR_ERR_DIS);
270 out_be32(&ddr->err_sbe, CONFIG_SYS_DDR_SBE);
274 out_be32(&ddr->sdram_cfg, CONFIG_SYS_DDR_CONTROL);
275 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
277 debug("DDR - 1st controller: memory initializing\n");
279 * Poll until memory is initialized.
280 * 512 Meg at 400 might hit this 200 times or so.
282 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
285 debug("DDR: memory initialized\n\n");
288 return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024;
293 * Initialize Local Bus
298 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
299 volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR);
305 get_sys_info(&sysinfo);
306 clkdiv = (lbc->lcrr & LCRR_CLKDIV) * 2;
307 lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv;
309 out_be32(&gur->lbiuiplldcr1, 0x00078080);
311 out_be32(&gur->lbiuiplldcr0, 0x7c0f1bf0);
312 else if (clkdiv == 8)
313 out_be32(&gur->lbiuiplldcr0, 0x6c0f1bf0);
314 else if (clkdiv == 4)
315 out_be32(&gur->lbiuiplldcr0, 0x5c0f1bf0);
317 out_be32(&lbc->lcrr, (u32)in_be32(&lbc->lcrr)| 0x00030000);
320 static void fdt_board_disable_serial(void *blob, bd_t *bd, const char *alias)
322 const char *status = "disabled";
326 off = fdt_path_offset(blob, alias);
328 printf("WARNING: could not find %s alias: %s.\n", alias,
333 err = fdt_setprop(blob, off, "status", status, strlen(status) + 1);
335 printf("WARNING: could not set status for serial0: %s.\n",
342 * Because of an erratum in prototype boards it is impossible to use eSDHC
343 * without disabling UART0 (which makes it quite easy to 'brick' the board
344 * by simply issung 'setenv hwconfig esdhc', and not able to interact with
347 * So, but default we assume that the board is a prototype, which is a most
348 * safe assumption. There is no way to determine board revision from a
349 * register, so we use hwconfig.
352 static int prototype_board(void)
354 if (hwconfig_subarg("board", "rev", NULL))
355 return hwconfig_subarg_cmp("board", "rev", "prototype");
359 static int esdhc_disables_uart0(void)
361 return prototype_board() ||
362 hwconfig_subarg_cmp("esdhc", "mode", "4-bits");
365 static void fdt_board_fixup_qe_uart(void *blob, bd_t *bd)
367 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
368 const char *devtype = "serial";
369 const char *compat = "ucc_uart";
370 const char *clk = "brg9";
374 if (!hwconfig("qe_uart"))
377 if (hwconfig("esdhc") && esdhc_disables_uart0()) {
378 printf("QE UART: won't enable with esdhc.\n");
382 fdt_board_disable_serial(blob, bd, "serial1");
388 off = fdt_node_offset_by_compatible(blob, off, "ucc_geth");
390 printf("WARNING: unable to fixup device tree for "
395 idx = fdt_getprop(blob, off, "cell-index", &len);
396 if (!idx || len != sizeof(*idx) || *idx != fdt32_to_cpu(2))
401 fdt_setprop(blob, off, "device_type", devtype, strlen(devtype) + 1);
402 fdt_setprop(blob, off, "compatible", compat, strlen(compat) + 1);
403 fdt_setprop(blob, off, "tx-clock-name", clk, strlen(clk) + 1);
404 fdt_setprop(blob, off, "rx-clock-name", clk, strlen(clk) + 1);
405 fdt_setprop(blob, off, "port-number", &portnum, sizeof(portnum));
407 setbits_8(&bcsr[15], BCSR15_QEUART_EN);
410 #ifdef CONFIG_FSL_ESDHC
412 int board_mmc_init(bd_t *bd)
414 struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
415 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR_BASE;
416 u8 bcsr6 = BCSR6_SD_CARD_1BIT;
418 if (!hwconfig("esdhc"))
421 printf("Enabling eSDHC...\n"
422 " For eSDHC to function, I2C2 ");
423 if (esdhc_disables_uart0()) {
424 printf("and UART0 should be disabled.\n");
425 printf(" Redirecting stderr, stdout and stdin to UART1...\n");
426 console_assign(stderr, "eserial1");
427 console_assign(stdout, "eserial1");
428 console_assign(stdin, "eserial1");
429 printf("Switched to UART1 (initial log has been printed to "
431 bcsr6 |= BCSR6_SD_CARD_4BITS;
433 printf("should be disabled.\n");
436 /* Assign I2C2 signals to eSDHC. */
437 clrsetbits_be32(&gur->plppar1, PLPPAR1_I2C_BIT_MASK,
439 clrsetbits_be32(&gur->plpdir1, PLPDIR1_I2C_BIT_MASK,
442 /* Mux I2C2 (and optionally UART0) signals to eSDHC. */
443 setbits_8(&bcsr[6], bcsr6);
445 return fsl_esdhc_mmc_init(bd);
448 static void fdt_board_fixup_esdhc(void *blob, bd_t *bd)
450 const char *status = "disabled";
453 if (!hwconfig("esdhc"))
456 if (esdhc_disables_uart0())
457 fdt_board_disable_serial(blob, bd, "serial0");
463 off = fdt_node_offset_by_compatible(blob, off, "fsl-i2c");
467 idx = fdt_getprop(blob, off, "cell-index", &len);
468 if (!idx || len != sizeof(*idx))
472 fdt_setprop(blob, off, "status", status,
479 static inline void fdt_board_fixup_esdhc(void *blob, bd_t *bd) {}
483 static struct pci_controller pcie1_hose;
484 #endif /* CONFIG_PCIE1 */
486 int first_free_busno = 0;
492 volatile ccsr_gur_t *gur;
496 gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
497 io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
498 host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
502 volatile ccsr_fsl_pci_t *pci;
503 struct pci_controller *hose;
505 struct pci_region *r;
508 pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
510 pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent);
512 pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
514 if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){
515 printf ("\n PCIE connected to slot as %s (base address %x)",
516 pcie_ep ? "End Point" : "Root Complex",
519 if (pci->pme_msg_det) {
520 pci->pme_msg_det = 0xffffffff;
521 debug (" with errors. Clearing. Now 0x%08x",
526 /* outbound memory */
528 CONFIG_SYS_PCIE1_MEM_BUS,
529 CONFIG_SYS_PCIE1_MEM_PHYS,
530 CONFIG_SYS_PCIE1_MEM_SIZE,
535 CONFIG_SYS_PCIE1_IO_BUS,
536 CONFIG_SYS_PCIE1_IO_PHYS,
537 CONFIG_SYS_PCIE1_IO_SIZE,
540 hose->region_count = r - hose->regions;
542 hose->first_busno=first_free_busno;
544 fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data);
545 printf ("PCIE on bus %02x - %02x\n",
546 hose->first_busno,hose->last_busno);
548 first_free_busno=hose->last_busno+1;
551 printf (" PCIE: disabled\n");
555 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
558 #endif /* CONFIG_PCI */
560 #if defined(CONFIG_OF_BOARD_SETUP)
561 void ft_board_setup(void *blob, bd_t *bd)
563 #if defined(CONFIG_SYS_UCC_RMII_MODE)
564 int nodeoff, off, err;
569 /* fixup device tree for supporting rmii mode */
571 while ((nodeoff = fdt_node_offset_by_compatible(blob, nodeoff,
573 err = fdt_setprop_string(blob, nodeoff, "tx-clock-name",
576 printf("WARNING: could not set tx-clock-name %s.\n",
581 err = fdt_setprop_string(blob, nodeoff, "phy-connection-type",
584 printf("WARNING: could not set phy-connection-type "
585 "%s.\n", fdt_strerror(err));
589 index = fdt_getprop(blob, nodeoff, "cell-index", 0);
591 printf("WARNING: could not get cell-index of ucc\n");
595 ph = fdt_getprop(blob, nodeoff, "phy-handle", 0);
597 printf("WARNING: could not get phy-handle of ucc\n");
601 off = fdt_node_offset_by_phandle(blob, *ph);
603 printf("WARNING: could not get phy node %s.\n",
608 val = 0x7 + *index; /* RMII phy address starts from 0x8 */
610 err = fdt_setprop(blob, off, "reg", &val, sizeof(u32));
612 printf("WARNING: could not set reg for phy-handle "
613 "%s.\n", fdt_strerror(err));
618 ft_cpu_setup(blob, bd);
621 ft_fsl_pci_setup(blob, "pci1", &pcie1_hose);
623 fdt_board_fixup_esdhc(blob, bd);
624 fdt_board_fixup_qe_uart(blob, bd);