1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2008, 2011 Freescale Semiconductor, Inc.
6 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
12 struct fsl_e_tlb_entry tlb_table[] = {
13 /* TLB 0 - for temp stack in cache */
14 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
15 MAS3_SX|MAS3_SW|MAS3_SR, 0,
16 0, 0, BOOKE_PAGESZ_4K, 0),
17 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
18 MAS3_SX|MAS3_SW|MAS3_SR, 0,
19 0, 0, BOOKE_PAGESZ_4K, 0),
20 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
21 MAS3_SX|MAS3_SW|MAS3_SR, 0,
22 0, 0, BOOKE_PAGESZ_4K, 0),
23 SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
24 MAS3_SX|MAS3_SW|MAS3_SR, 0,
25 0, 0, BOOKE_PAGESZ_4K, 0),
30 * FLASH(cover boot page) 16M Non-cacheable, guarded
32 SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
33 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
34 0, 0, BOOKE_PAGESZ_16M, 1),
38 * CCSRBAR 1M Non-cacheable, guarded
40 SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
41 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
42 0, 1, BOOKE_PAGESZ_1M, 1),
46 * LBC SDRAM 64M Cacheable, non-guarded
48 SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE,
49 CONFIG_SYS_LBC_SDRAM_BASE_PHYS,
50 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
51 0, 2, BOOKE_PAGESZ_64M, 1),
55 * CADMUS registers 1M Non-cacheable, guarded
57 SET_TLB_ENTRY(1, CADMUS_BASE_ADDR, CADMUS_BASE_ADDR_PHYS,
58 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
59 0, 3, BOOKE_PAGESZ_1M, 1),
63 * PCI and PCIe MEM 1G Non-cacheable, guarded
65 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS,
66 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
67 0, 4, BOOKE_PAGESZ_1G, 1),
71 * PCI1 IO 1M Non-cacheable, guarded
73 SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_IO_VIRT, CONFIG_SYS_PCI1_IO_PHYS,
74 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
75 0, 5, BOOKE_PAGESZ_1M, 1),
79 * PCIe IO 1M Non-cacheable, guarded
81 SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS,
82 MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
83 0, 6, BOOKE_PAGESZ_1M, 1),
86 int num_tlb_entries = ARRAY_SIZE(tlb_table);