board/freescale/mpc8544ds/tlb.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2008 Freescale Semiconductor, Inc.
   4  *
   5  * (C) Copyright 2000
   6  * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
   7  */
   8
   9 #include <common.h>
  10 #include <asm/mmu.h>
  11
  12 struct fsl_e_tlb_entry tlb_table[] = {
  13         /* TLB 0 - for temp stack in cache */
  14         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  15                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  16                       0, 0, BOOKE_PAGESZ_4K, 0),
  17         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  18                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19                       0, 0, BOOKE_PAGESZ_4K, 0),
  20         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  21                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  22                       0, 0, BOOKE_PAGESZ_4K, 0),
  23         SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  24                       MAS3_SX|MAS3_SW|MAS3_SR, 0,
  25                       0, 0, BOOKE_PAGESZ_4K, 0),
  26         /*
  27          * TLB 0:       64M     Non-cacheable, guarded
  28          * 0xfc000000   64M     Covers FLASH at 0xFE800000 and 0xFF800000
  29          * Out of reset this entry is only 4K.
  30          */
  31         SET_TLB_ENTRY(1, CONFIG_SYS_BOOT_BLOCK, CONFIG_SYS_BOOT_BLOCK,
  32                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  33                       0, 0, BOOKE_PAGESZ_64M, 1),
  34         /*
  35          * TLB 1:       1G      Non-cacheable, guarded
  36          * 0x80000000   1G      PCIE  8,9,a,b
  37          */
  38         SET_TLB_ENTRY(1, CONFIG_SYS_PCIE_VIRT, CONFIG_SYS_PCIE_PHYS,
  39                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  40                       0, 1, BOOKE_PAGESZ_1G, 1),
  41
  42         /*
  43          * TLB 2:       256M    Non-cacheable, guarded
  44          */
  45         SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT, CONFIG_SYS_PCI_PHYS,
  46                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  47                       0, 2, BOOKE_PAGESZ_256M, 1),
  48
  49         /*
  50          * TLB 3:       256M    Non-cacheable, guarded
  51          */
  52         SET_TLB_ENTRY(1, CONFIG_SYS_PCI_VIRT + 0x10000000, CONFIG_SYS_PCI_PHYS + 0x10000000,
  53                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54                       0, 3, BOOKE_PAGESZ_256M, 1),
  55
  56         /*
  57          * TLB 4:       64M     Non-cacheable, guarded
  58          * 0xe000_0000  1M      CCSRBAR
  59          * 0xe100_0000  255M    PCI IO range
  60          */
  61         SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  62                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  63                       0, 4, BOOKE_PAGESZ_64M, 1),
  64
  65         /*
  66          * TLB 5:       64M     Non-cacheable, guarded
  67          * 0xf8000000   64M     PIXIS 0xF8000000 - 0xFBFFFFFF
  68          */
  69         SET_TLB_ENTRY(1, CONFIG_SYS_LBC_NONCACHE_BASE, CONFIG_SYS_LBC_NONCACHE_BASE,
  70                       MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  71                       0, 5, BOOKE_PAGESZ_64M, 1),
  72 };
  73
  74 int num_tlb_entries = ARRAY_SIZE(tlb_table);