2 * Copyright 2007 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
27 #include <asm/immap_85xx.h>
28 #include <asm/immap_fsl_pci.h>
30 #include <spd_sdram.h>
33 #include <fdt_support.h>
35 #include "../common/pixis.h"
37 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
38 extern void ddr_enable_ecc(unsigned int dram_size);
41 void sdram_init(void);
45 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
46 volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR);
47 volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR);
49 if ((uint)&gur->porpllsr != 0xe00e0000) {
50 printf("immap size error %lx\n",(ulong)&gur->porpllsr);
52 printf ("Board: MPC8544DS, System ID: 0x%02x, "
53 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
54 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
55 in8(PIXIS_BASE + PIXIS_PVER));
57 lbc->ltesr = 0xffffffff; /* Clear LBC error interrupts */
58 lbc->lteir = 0xffffffff; /* Enable LBC error interrupts */
59 ecm->eedr = 0xffffffff; /* Clear ecm errors */
60 ecm->eeer = 0xffffffff; /* Enable ecm errors */
66 initdram(int board_type)
70 puts("Initializing\n");
72 dram_size = spd_sdram();
74 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
76 * Initialize and enable DDR ECC.
78 ddr_enable_ecc(dram_size);
85 static struct pci_controller pci1_hose;
89 static struct pci_controller pcie1_hose;
93 static struct pci_controller pcie2_hose;
97 static struct pci_controller pcie3_hose;
100 int first_free_busno=0;
105 volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR);
106 uint devdisr = gur->devdisr;
107 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
108 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
110 debug (" pci_init_board: devdisr=%x, io_sel=%x, host_agent=%x\n",
111 devdisr, io_sel, host_agent);
114 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII1_DIS))
115 printf (" eTSEC1 is in sgmii mode.\n");
116 if (!(gur->pordevsr & MPC85xx_PORDEVSR_SGMII3_DIS))
117 printf (" eTSEC3 is in sgmii mode.\n");
122 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE3_ADDR;
123 extern void fsl_pci_init(struct pci_controller *hose);
124 struct pci_controller *hose = &pcie3_hose;
125 int pcie_ep = (host_agent == 1);
126 int pcie_configured = io_sel >= 1;
128 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
129 printf ("\n PCIE3 connected to ULI as %s (base address %x)",
130 pcie_ep ? "End Point" : "Root Complex",
132 if (pci->pme_msg_det) {
133 pci->pme_msg_det = 0xffffffff;
134 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
139 pci_set_region(hose->regions + 0,
143 PCI_REGION_MEM | PCI_REGION_MEMORY);
145 /* outbound memory */
146 pci_set_region(hose->regions + 1,
153 pci_set_region(hose->regions + 2,
159 hose->region_count = 3;
160 #ifdef CFG_PCIE3_MEM_BASE2
161 /* outbound memory */
162 pci_set_region(hose->regions + 3,
167 hose->region_count++;
169 hose->first_busno=first_free_busno;
170 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
174 first_free_busno=hose->last_busno+1;
175 printf (" PCIE3 on bus %02x - %02x\n",
176 hose->first_busno,hose->last_busno);
179 * Activate ULI1575 legacy chip by performing a fake
180 * memory access. Needed to make ULI RTC work.
182 in_be32((u32 *)CFG_PCIE3_MEM_BASE);
184 printf (" PCIE3: disabled\n");
189 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
194 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE1_ADDR;
195 extern void fsl_pci_init(struct pci_controller *hose);
196 struct pci_controller *hose = &pcie1_hose;
197 int pcie_ep = (host_agent == 5);
198 int pcie_configured = io_sel & 6;
200 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
201 printf ("\n PCIE1 connected to Slot2 as %s (base address %x)",
202 pcie_ep ? "End Point" : "Root Complex",
204 if (pci->pme_msg_det) {
205 pci->pme_msg_det = 0xffffffff;
206 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
211 pci_set_region(hose->regions + 0,
215 PCI_REGION_MEM | PCI_REGION_MEMORY);
217 /* outbound memory */
218 pci_set_region(hose->regions + 1,
225 pci_set_region(hose->regions + 2,
231 hose->region_count = 3;
232 #ifdef CFG_PCIE1_MEM_BASE2
233 /* outbound memory */
234 pci_set_region(hose->regions + 3,
239 hose->region_count++;
241 hose->first_busno=first_free_busno;
243 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
247 first_free_busno=hose->last_busno+1;
248 printf(" PCIE1 on bus %02x - %02x\n",
249 hose->first_busno,hose->last_busno);
252 printf (" PCIE1: disabled\n");
257 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
262 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCIE2_ADDR;
263 extern void fsl_pci_init(struct pci_controller *hose);
264 struct pci_controller *hose = &pcie2_hose;
265 int pcie_ep = (host_agent == 3);
266 int pcie_configured = io_sel & 4;
268 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
269 printf ("\n PCIE2 connected to Slot 1 as %s (base address %x)",
270 pcie_ep ? "End Point" : "Root Complex",
272 if (pci->pme_msg_det) {
273 pci->pme_msg_det = 0xffffffff;
274 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
279 pci_set_region(hose->regions + 0,
283 PCI_REGION_MEM | PCI_REGION_MEMORY);
285 /* outbound memory */
286 pci_set_region(hose->regions + 1,
293 pci_set_region(hose->regions + 2,
299 hose->region_count = 3;
300 #ifdef CFG_PCIE2_MEM_BASE2
301 /* outbound memory */
302 pci_set_region(hose->regions + 3,
307 hose->region_count++;
309 hose->first_busno=first_free_busno;
310 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
313 first_free_busno=hose->last_busno+1;
314 printf (" PCIE2 on bus %02x - %02x\n",
315 hose->first_busno,hose->last_busno);
318 printf (" PCIE2: disabled\n");
323 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
329 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CFG_PCI1_ADDR;
330 extern void fsl_pci_init(struct pci_controller *hose);
331 struct pci_controller *hose = &pci1_hose;
333 uint pci_agent = (host_agent == 6);
334 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
336 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
337 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
340 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
341 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
343 (pci_speed == 33333000) ? "33" :
344 (pci_speed == 66666000) ? "66" : "unknown",
345 pci_clk_sel ? "sync" : "async",
346 pci_agent ? "agent" : "host",
347 pci_arb ? "arbiter" : "external-arbiter",
352 pci_set_region(hose->regions + 0,
356 PCI_REGION_MEM | PCI_REGION_MEMORY);
358 /* outbound memory */
359 pci_set_region(hose->regions + 1,
366 pci_set_region(hose->regions + 2,
371 hose->region_count = 3;
372 #ifdef CFG_PCIE3_MEM_BASE2
373 /* outbound memory */
374 pci_set_region(hose->regions + 3,
379 hose->region_count++;
381 hose->first_busno=first_free_busno;
382 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
385 first_free_busno=hose->last_busno+1;
386 printf ("PCI on bus %02x - %02x\n",
387 hose->first_busno,hose->last_busno);
389 printf (" PCI: disabled\n");
393 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
398 int last_stage_init(void)
405 get_board_sys_clk(ulong dummy)
407 u8 i, go_bit, rd_clks;
410 go_bit = in8(PIXIS_BASE + PIXIS_VCTL);
413 rd_clks = in8(PIXIS_BASE + PIXIS_VCFGEN0);
417 * Only if both go bit and the SCLK bit in VCFGEN0 are set
418 * should we be using the AUX register. Remember, we also set the
419 * GO bit to boot from the alternate bank on the on-board flash
424 i = in8(PIXIS_BASE + PIXIS_AUX);
426 i = in8(PIXIS_BASE + PIXIS_SPD);
428 i = in8(PIXIS_BASE + PIXIS_SPD);
463 #if defined(CONFIG_OF_BOARD_SETUP)
466 ft_board_setup(void *blob, bd_t *bd)
471 ft_cpu_setup(blob, bd);
473 node = fdt_path_offset(blob, "/aliases");
477 path = fdt_getprop(blob, node, "pci0", NULL);
479 tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno;
480 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
484 path = fdt_getprop(blob, node, "pci1", NULL);
486 tmp[1] = pcie2_hose.last_busno - pcie2_hose.first_busno;
487 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
491 path = fdt_getprop(blob, node, "pci2", NULL);
493 tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno;
494 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);
498 path = fdt_getprop(blob, node, "pci3", NULL);
500 tmp[1] = pcie3_hose.last_busno - pcie3_hose.first_busno;
501 do_fixup_by_path(blob, path, "bus-range", &tmp, 8, 1);