2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
36 #include <spd_sdram.h>
37 #include <fdt_support.h>
41 #include "../common/pixis.h"
42 #include "../common/sgmii_riser.h"
44 phys_size_t fixed_sdram(void);
48 printf ("Board: MPC8536DS, System ID: 0x%02x, "
49 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
50 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
51 in8(PIXIS_BASE + PIXIS_PVER));
56 initdram(int board_type)
58 phys_size_t dram_size = 0;
60 puts("Initializing....");
62 #ifdef CONFIG_SPD_EEPROM
63 dram_size = fsl_ddr_sdram();
65 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
67 dram_size *= 0x100000;
69 dram_size = fixed_sdram();
76 #if !defined(CONFIG_SPD_EEPROM)
78 * Fixed sdram init -- doesn't use serial presence detect.
81 phys_size_t fixed_sdram (void)
83 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
84 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
87 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
88 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
90 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
91 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
92 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
93 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
94 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
95 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
96 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
97 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
98 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
99 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
101 #if defined (CONFIG_DDR_ECC)
102 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
103 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
104 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
110 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
112 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
114 debug("DDR - 1st controller: memory initializing\n");
116 * Poll until memory is initialized.
117 * 512 Meg at 400 might hit this 200 times or so.
119 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
122 debug("DDR: memory initialized\n\n");
127 return 512 * 1024 * 1024;
133 static struct pci_controller pci1_hose;
137 static struct pci_controller pcie1_hose;
141 static struct pci_controller pcie2_hose;
145 static struct pci_controller pcie3_hose;
148 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
149 extern void fsl_pci_init(struct pci_controller *hose);
151 int first_free_busno=0;
156 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
157 uint devdisr = gur->devdisr;
159 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
160 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
161 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
163 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
164 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
166 if (sdrs2_io_sel == 7)
167 printf(" Serdes2 disalbed\n");
168 else if (sdrs2_io_sel == 4) {
169 printf(" eTSEC1 is in sgmii mode.\n");
170 printf(" eTSEC3 is in sgmii mode.\n");
171 } else if (sdrs2_io_sel == 6)
172 printf(" eTSEC1 is in sgmii mode.\n");
176 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
177 struct pci_controller *hose = &pcie3_hose;
178 int pcie_ep = (host_agent == 1);
179 int pcie_configured = (io_sel == 7);
180 struct pci_region *r = hose->regions;
182 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
183 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
184 pcie_ep ? "End Point" : "Root Complex",
186 if (pci->pme_msg_det) {
187 pci->pme_msg_det = 0xffffffff;
188 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
193 r += fsl_pci_setup_inbound_windows(r);
195 /* outbound memory */
197 CONFIG_SYS_PCIE3_MEM_BASE,
198 CONFIG_SYS_PCIE3_MEM_PHYS,
199 CONFIG_SYS_PCIE3_MEM_SIZE,
204 CONFIG_SYS_PCIE3_IO_BASE,
205 CONFIG_SYS_PCIE3_IO_PHYS,
206 CONFIG_SYS_PCIE3_IO_SIZE,
209 hose->region_count = r - hose->regions;
211 hose->first_busno=first_free_busno;
212 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
216 first_free_busno=hose->last_busno+1;
217 printf (" PCIE3 on bus %02x - %02x\n",
218 hose->first_busno,hose->last_busno);
220 printf (" PCIE3: disabled\n");
225 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
230 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
231 struct pci_controller *hose = &pcie1_hose;
232 int pcie_ep = (host_agent == 5);
233 int pcie_configured = (io_sel == 2 || io_sel == 3
234 || io_sel == 5 || io_sel == 7);
235 struct pci_region *r = hose->regions;
237 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
238 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
239 pcie_ep ? "End Point" : "Root Complex",
241 if (pci->pme_msg_det) {
242 pci->pme_msg_det = 0xffffffff;
243 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
248 r += fsl_pci_setup_inbound_windows(r);
250 /* outbound memory */
252 CONFIG_SYS_PCIE1_MEM_BASE,
253 CONFIG_SYS_PCIE1_MEM_PHYS,
254 CONFIG_SYS_PCIE1_MEM_SIZE,
259 CONFIG_SYS_PCIE1_IO_BASE,
260 CONFIG_SYS_PCIE1_IO_PHYS,
261 CONFIG_SYS_PCIE1_IO_SIZE,
264 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
265 /* outbound memory */
267 CONFIG_SYS_PCIE1_MEM_BASE2,
268 CONFIG_SYS_PCIE1_MEM_PHYS2,
269 CONFIG_SYS_PCIE1_MEM_SIZE2,
272 hose->region_count = r - hose->regions;
273 hose->first_busno=first_free_busno;
275 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
279 first_free_busno=hose->last_busno+1;
280 printf(" PCIE1 on bus %02x - %02x\n",
281 hose->first_busno,hose->last_busno);
284 printf (" PCIE1: disabled\n");
289 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
294 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
295 struct pci_controller *hose = &pcie2_hose;
296 int pcie_ep = (host_agent == 3);
297 int pcie_configured = (io_sel == 5 || io_sel == 7);
298 struct pci_region *r = hose->regions;
300 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
301 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
302 pcie_ep ? "End Point" : "Root Complex",
304 if (pci->pme_msg_det) {
305 pci->pme_msg_det = 0xffffffff;
306 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
311 r += fsl_pci_setup_inbound_windows(r);
313 /* outbound memory */
315 CONFIG_SYS_PCIE2_MEM_BASE,
316 CONFIG_SYS_PCIE2_MEM_PHYS,
317 CONFIG_SYS_PCIE2_MEM_SIZE,
322 CONFIG_SYS_PCIE2_IO_BASE,
323 CONFIG_SYS_PCIE2_IO_PHYS,
324 CONFIG_SYS_PCIE2_IO_SIZE,
327 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
328 /* outbound memory */
330 CONFIG_SYS_PCIE2_MEM_BASE2,
331 CONFIG_SYS_PCIE2_MEM_PHYS2,
332 CONFIG_SYS_PCIE2_MEM_SIZE2,
335 hose->region_count = r - hose->regions;
336 hose->first_busno=first_free_busno;
337 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
340 first_free_busno=hose->last_busno+1;
341 printf (" PCIE2 on bus %02x - %02x\n",
342 hose->first_busno,hose->last_busno);
345 printf (" PCIE2: disabled\n");
350 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
356 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
357 struct pci_controller *hose = &pci1_hose;
358 struct pci_region *r = hose->regions;
360 uint pci_agent = (host_agent == 6);
361 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
363 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
364 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
367 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
368 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
370 (pci_speed == 33333000) ? "33" :
371 (pci_speed == 66666000) ? "66" : "unknown",
372 pci_clk_sel ? "sync" : "async",
373 pci_agent ? "agent" : "host",
374 pci_arb ? "arbiter" : "external-arbiter",
379 r += fsl_pci_setup_inbound_windows(r);
381 /* outbound memory */
383 CONFIG_SYS_PCI1_MEM_BASE,
384 CONFIG_SYS_PCI1_MEM_PHYS,
385 CONFIG_SYS_PCI1_MEM_SIZE,
390 CONFIG_SYS_PCI1_IO_BASE,
391 CONFIG_SYS_PCI1_IO_PHYS,
392 CONFIG_SYS_PCI1_IO_SIZE,
395 #ifdef CONFIG_SYS_PCI1_MEM_BASE2
396 /* outbound memory */
398 CONFIG_SYS_PCI1_MEM_BASE2,
399 CONFIG_SYS_PCI1_MEM_PHYS2,
400 CONFIG_SYS_PCI1_MEM_SIZE2,
403 hose->region_count = r - hose->regions;
404 hose->first_busno=first_free_busno;
405 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
408 first_free_busno=hose->last_busno+1;
409 printf ("PCI on bus %02x - %02x\n",
410 hose->first_busno,hose->last_busno);
412 printf (" PCI: disabled\n");
416 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
421 int board_early_init_r(void)
423 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
424 const u8 flash_esel = 1;
427 * Remap Boot flash + PROMJET region to caching-inhibited
428 * so that flash can be erased properly.
431 /* Flush d-cache and invalidate i-cache of any FLASH data */
435 /* invalidate existing TLB entry for flash + promjet */
436 disable_tlb(flash_esel);
438 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
439 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
440 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
445 #ifdef CONFIG_GET_CLK_FROM_ICS307
446 /* decode S[0-2] to Output Divider (OD) */
449 10, 2, 8, 4, 5, 7, 3, 6
452 /* Calculate frequency being generated by ICS307-02 clock chip based upon
453 * the control bytes being programmed into it. */
454 /* XXX: This function should probably go into a common library */
456 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
458 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
459 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
460 unsigned long RDW = cw2 & 0x7F;
461 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
464 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
466 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
467 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
468 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
470 * R6:R0 = Reference Divider Word (RDW)
471 * V8:V0 = VCO Divider Word (VDW)
472 * S2:S0 = Output Divider Select (OD)
473 * F1:F0 = Function of CLK2 Output
475 * C1:C0 = internal load capacitance for cyrstal
478 /* Adding 1 to get a "nicely" rounded number, but this needs
479 * more tweaking to get a "properly" rounded number. */
481 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
483 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
489 get_board_sys_clk(ulong dummy)
491 return ics307_clk_freq (
492 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
493 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
494 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
499 get_board_ddr_clk(ulong dummy)
501 return ics307_clk_freq (
502 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
503 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
504 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
509 get_board_sys_clk(ulong dummy)
514 i = in8(PIXIS_BASE + PIXIS_SPD);
548 get_board_ddr_clk(ulong dummy)
553 i = in8(PIXIS_BASE + PIXIS_SPD);
587 int is_sata_supported(void)
589 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
591 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
592 if (sdrs2_io_sel & 0x04)
598 int board_eth_init(bd_t *bis)
600 #ifdef CONFIG_TSEC_ENET
601 struct tsec_info_struct tsec_info[2];
602 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
605 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
608 SET_STD_TSEC_INFO(tsec_info[num], 1);
609 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
610 tsec_info[num].phyaddr = 0;
611 tsec_info[num].flags |= TSEC_SGMII;
616 SET_STD_TSEC_INFO(tsec_info[num], 3);
617 if (sdrs2_io_sel == 4) {
618 tsec_info[num].phyaddr = 1;
619 tsec_info[num].flags |= TSEC_SGMII;
625 printf("No TSECs initialized\n");
629 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
630 fsl_sgmii_riser_init(tsec_info, num);
632 tsec_eth_init(bis, tsec_info, num);
634 return pci_eth_init(bis);
637 #if defined(CONFIG_OF_BOARD_SETUP)
638 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
639 struct pci_controller *hose);
641 void ft_board_setup(void *blob, bd_t *bd)
643 ft_cpu_setup(blob, bd);
646 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
649 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
652 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
655 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);