2 * Copyright 2008 Freescale Semiconductor.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/immap_fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
36 #include <spd_sdram.h>
37 #include <fdt_support.h>
41 #include "../common/pixis.h"
42 #include "../common/sgmii_riser.h"
44 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
45 extern void ddr_enable_ecc(unsigned int dram_size);
48 phys_size_t fixed_sdram(void);
52 printf ("Board: MPC8536DS, System ID: 0x%02x, "
53 "System Version: 0x%02x, FPGA Version: 0x%02x\n",
54 in8(PIXIS_BASE + PIXIS_ID), in8(PIXIS_BASE + PIXIS_VER),
55 in8(PIXIS_BASE + PIXIS_PVER));
60 initdram(int board_type)
62 phys_size_t dram_size = 0;
64 puts("Initializing....");
66 #ifdef CONFIG_SPD_EEPROM
67 dram_size = fsl_ddr_sdram();
69 dram_size = setup_ddr_tlbs(dram_size / 0x100000);
71 dram_size *= 0x100000;
73 dram_size = fixed_sdram();
76 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
78 * Initialize and enable DDR ECC.
80 ddr_enable_ecc(dram_size);
86 #if !defined(CONFIG_SPD_EEPROM)
88 * Fixed sdram init -- doesn't use serial presence detect.
91 phys_size_t fixed_sdram (void)
93 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
94 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
97 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
98 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
100 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
101 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
102 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
103 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
104 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
105 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
106 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
107 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
108 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
109 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
111 #if defined (CONFIG_DDR_ECC)
112 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
113 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
114 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
120 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
122 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
124 debug("DDR - 1st controller: memory initializing\n");
126 * Poll until memory is initialized.
127 * 512 Meg at 400 might hit this 200 times or so.
129 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
132 debug("DDR: memory initialized\n\n");
137 return 512 * 1024 * 1024;
143 static struct pci_controller pci1_hose;
147 static struct pci_controller pcie1_hose;
151 static struct pci_controller pcie2_hose;
155 static struct pci_controller pcie3_hose;
158 extern int fsl_pci_setup_inbound_windows(struct pci_region *r);
159 extern void fsl_pci_init(struct pci_controller *hose);
161 int first_free_busno=0;
166 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
167 uint devdisr = gur->devdisr;
169 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
170 uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
171 uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16;
173 debug(" pci_init_board: devdisr=%x, sdrs2_io_sel=%x, io_sel=%x,\
174 host_agent=%x\n", devdisr, sdrs2_io_sel, io_sel, host_agent);
176 if (sdrs2_io_sel == 7)
177 printf(" Serdes2 disalbed\n");
178 else if (sdrs2_io_sel == 4) {
179 printf(" eTSEC1 is in sgmii mode.\n");
180 printf(" eTSEC3 is in sgmii mode.\n");
181 } else if (sdrs2_io_sel == 6)
182 printf(" eTSEC1 is in sgmii mode.\n");
186 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE3_ADDR;
187 struct pci_controller *hose = &pcie3_hose;
188 int pcie_ep = (host_agent == 1);
189 int pcie_configured = (io_sel == 7);
190 struct pci_region *r = hose->regions;
192 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
193 printf ("\n PCIE3 connected to Slot3 as %s (base address %x)",
194 pcie_ep ? "End Point" : "Root Complex",
196 if (pci->pme_msg_det) {
197 pci->pme_msg_det = 0xffffffff;
198 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
203 r += fsl_pci_setup_inbound_windows(r);
205 /* outbound memory */
207 CONFIG_SYS_PCIE3_MEM_BASE,
208 CONFIG_SYS_PCIE3_MEM_PHYS,
209 CONFIG_SYS_PCIE3_MEM_SIZE,
214 CONFIG_SYS_PCIE3_IO_BASE,
215 CONFIG_SYS_PCIE3_IO_PHYS,
216 CONFIG_SYS_PCIE3_IO_SIZE,
219 hose->region_count = r - hose->regions;
221 hose->first_busno=first_free_busno;
222 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
226 first_free_busno=hose->last_busno+1;
227 printf (" PCIE3 on bus %02x - %02x\n",
228 hose->first_busno,hose->last_busno);
230 printf (" PCIE3: disabled\n");
235 gur->devdisr |= MPC85xx_DEVDISR_PCIE3; /* disable */
240 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR;
241 struct pci_controller *hose = &pcie1_hose;
242 int pcie_ep = (host_agent == 5);
243 int pcie_configured = (io_sel == 2 || io_sel == 3
244 || io_sel == 5 || io_sel == 7);
245 struct pci_region *r = hose->regions;
247 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
248 printf ("\n PCIE1 connected to Slot1 as %s (base address %x)",
249 pcie_ep ? "End Point" : "Root Complex",
251 if (pci->pme_msg_det) {
252 pci->pme_msg_det = 0xffffffff;
253 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
258 r += fsl_pci_setup_inbound_windows(r);
260 /* outbound memory */
262 CONFIG_SYS_PCIE1_MEM_BASE,
263 CONFIG_SYS_PCIE1_MEM_PHYS,
264 CONFIG_SYS_PCIE1_MEM_SIZE,
269 CONFIG_SYS_PCIE1_IO_BASE,
270 CONFIG_SYS_PCIE1_IO_PHYS,
271 CONFIG_SYS_PCIE1_IO_SIZE,
274 #ifdef CONFIG_SYS_PCIE1_MEM_BASE2
275 /* outbound memory */
277 CONFIG_SYS_PCIE1_MEM_BASE2,
278 CONFIG_SYS_PCIE1_MEM_PHYS2,
279 CONFIG_SYS_PCIE1_MEM_SIZE2,
282 hose->region_count = r - hose->regions;
283 hose->first_busno=first_free_busno;
285 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
289 first_free_busno=hose->last_busno+1;
290 printf(" PCIE1 on bus %02x - %02x\n",
291 hose->first_busno,hose->last_busno);
294 printf (" PCIE1: disabled\n");
299 gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */
304 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE2_ADDR;
305 struct pci_controller *hose = &pcie2_hose;
306 int pcie_ep = (host_agent == 3);
307 int pcie_configured = (io_sel == 5 || io_sel == 7);
308 struct pci_region *r = hose->regions;
310 if (pcie_configured && !(devdisr & MPC85xx_DEVDISR_PCIE)){
311 printf ("\n PCIE2 connected to Slot 2 as %s (base address %x)",
312 pcie_ep ? "End Point" : "Root Complex",
314 if (pci->pme_msg_det) {
315 pci->pme_msg_det = 0xffffffff;
316 debug (" with errors. Clearing. Now 0x%08x",pci->pme_msg_det);
321 r += fsl_pci_setup_inbound_windows(r);
323 /* outbound memory */
325 CONFIG_SYS_PCIE2_MEM_BASE,
326 CONFIG_SYS_PCIE2_MEM_PHYS,
327 CONFIG_SYS_PCIE2_MEM_SIZE,
332 CONFIG_SYS_PCIE2_IO_BASE,
333 CONFIG_SYS_PCIE2_IO_PHYS,
334 CONFIG_SYS_PCIE2_IO_SIZE,
337 #ifdef CONFIG_SYS_PCIE2_MEM_BASE2
338 /* outbound memory */
340 CONFIG_SYS_PCIE2_MEM_BASE2,
341 CONFIG_SYS_PCIE2_MEM_PHYS2,
342 CONFIG_SYS_PCIE2_MEM_SIZE2,
345 hose->region_count = r - hose->regions;
346 hose->first_busno=first_free_busno;
347 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
350 first_free_busno=hose->last_busno+1;
351 printf (" PCIE2 on bus %02x - %02x\n",
352 hose->first_busno,hose->last_busno);
355 printf (" PCIE2: disabled\n");
360 gur->devdisr |= MPC85xx_DEVDISR_PCIE2; /* disable */
366 volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR;
367 struct pci_controller *hose = &pci1_hose;
368 struct pci_region *r = hose->regions;
370 uint pci_agent = (host_agent == 6);
371 uint pci_speed = 66666000; /*get_clock_freq (); PCI PSPEED in [4:5] */
373 uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */
374 uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
377 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
378 printf ("\n PCI: %d bit, %s MHz, %s, %s, %s (base address %x)\n",
380 (pci_speed == 33333000) ? "33" :
381 (pci_speed == 66666000) ? "66" : "unknown",
382 pci_clk_sel ? "sync" : "async",
383 pci_agent ? "agent" : "host",
384 pci_arb ? "arbiter" : "external-arbiter",
389 r += fsl_pci_setup_inbound_windows(r);
391 /* outbound memory */
393 CONFIG_SYS_PCI1_MEM_BASE,
394 CONFIG_SYS_PCI1_MEM_PHYS,
395 CONFIG_SYS_PCI1_MEM_SIZE,
400 CONFIG_SYS_PCI1_IO_BASE,
401 CONFIG_SYS_PCI1_IO_PHYS,
402 CONFIG_SYS_PCI1_IO_SIZE,
405 #ifdef CONFIG_SYS_PCI1_MEM_BASE2
406 /* outbound memory */
408 CONFIG_SYS_PCI1_MEM_BASE2,
409 CONFIG_SYS_PCI1_MEM_PHYS2,
410 CONFIG_SYS_PCI1_MEM_SIZE2,
413 hose->region_count = r - hose->regions;
414 hose->first_busno=first_free_busno;
415 pci_setup_indirect(hose, (int) &pci->cfg_addr, (int) &pci->cfg_data);
418 first_free_busno=hose->last_busno+1;
419 printf ("PCI on bus %02x - %02x\n",
420 hose->first_busno,hose->last_busno);
422 printf (" PCI: disabled\n");
426 gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */
431 int board_early_init_r(void)
433 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
434 const u8 flash_esel = 1;
437 * Remap Boot flash + PROMJET region to caching-inhibited
438 * so that flash can be erased properly.
441 /* Flush d-cache and invalidate i-cache of any FLASH data */
445 /* invalidate existing TLB entry for flash + promjet */
446 disable_tlb(flash_esel);
448 set_tlb(1, flashbase, flashbase, /* tlb, epn, rpn */
449 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
450 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
455 #ifdef CONFIG_GET_CLK_FROM_ICS307
456 /* decode S[0-2] to Output Divider (OD) */
459 10, 2, 8, 4, 5, 7, 3, 6
462 /* Calculate frequency being generated by ICS307-02 clock chip based upon
463 * the control bytes being programmed into it. */
464 /* XXX: This function should probably go into a common library */
466 ics307_clk_freq (unsigned char cw0, unsigned char cw1, unsigned char cw2)
468 const unsigned long long InputFrequency = CONFIG_ICS307_REFCLK_HZ;
469 unsigned long VDW = ((cw1 << 1) & 0x1FE) + ((cw2 >> 7) & 1);
470 unsigned long RDW = cw2 & 0x7F;
471 unsigned long OD = ics307_S_to_OD[cw0 & 0x7];
474 /* CLK1Frequency = InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD) */
476 /* cw0: C1 C0 TTL F1 F0 S2 S1 S0
477 * cw1: V8 V7 V6 V5 V4 V3 V2 V1
478 * cw2: V0 R6 R5 R4 R3 R2 R1 R0
480 * R6:R0 = Reference Divider Word (RDW)
481 * V8:V0 = VCO Divider Word (VDW)
482 * S2:S0 = Output Divider Select (OD)
483 * F1:F0 = Function of CLK2 Output
485 * C1:C0 = internal load capacitance for cyrstal
488 /* Adding 1 to get a "nicely" rounded number, but this needs
489 * more tweaking to get a "properly" rounded number. */
491 freq = 1 + (InputFrequency * 2 * (VDW + 8) / ((RDW + 2) * OD));
493 debug("ICS307: CW[0-2]: %02X %02X %02X => %u Hz\n", cw0, cw1, cw2,
499 get_board_sys_clk(ulong dummy)
501 return ics307_clk_freq (
502 in8(PIXIS_BASE + PIXIS_VSYSCLK0),
503 in8(PIXIS_BASE + PIXIS_VSYSCLK1),
504 in8(PIXIS_BASE + PIXIS_VSYSCLK2)
509 get_board_ddr_clk(ulong dummy)
511 return ics307_clk_freq (
512 in8(PIXIS_BASE + PIXIS_VDDRCLK0),
513 in8(PIXIS_BASE + PIXIS_VDDRCLK1),
514 in8(PIXIS_BASE + PIXIS_VDDRCLK2)
519 get_board_sys_clk(ulong dummy)
524 i = in8(PIXIS_BASE + PIXIS_SPD);
558 get_board_ddr_clk(ulong dummy)
563 i = in8(PIXIS_BASE + PIXIS_SPD);
597 int is_sata_supported(void)
599 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
601 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
602 if (sdrs2_io_sel & 0x04)
608 int board_eth_init(bd_t *bis)
610 #ifdef CONFIG_TSEC_ENET
611 struct tsec_info_struct tsec_info[2];
612 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
615 (gur->pordevsr & MPC85xx_PORDEVSR_SRDS2_IO_SEL) >> 27;
618 SET_STD_TSEC_INFO(tsec_info[num], 1);
619 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6)) {
620 tsec_info[num].phyaddr = 0;
621 tsec_info[num].flags |= TSEC_SGMII;
626 SET_STD_TSEC_INFO(tsec_info[num], 3);
627 if (sdrs2_io_sel == 4) {
628 tsec_info[num].phyaddr = 1;
629 tsec_info[num].flags |= TSEC_SGMII;
635 printf("No TSECs initialized\n");
639 if ((sdrs2_io_sel == 4) || (sdrs2_io_sel == 6))
640 fsl_sgmii_riser_init(tsec_info, num);
642 tsec_eth_init(bis, tsec_info, num);
644 return pci_eth_init(bis);
647 #if defined(CONFIG_OF_BOARD_SETUP)
648 extern void ft_fsl_pci_setup(void *blob, const char *pci_alias,
649 struct pci_controller *hose);
651 void ft_board_setup(void *blob, bd_t *bd)
653 ft_cpu_setup(blob, bd);
656 ft_fsl_pci_setup(blob, "pci0", &pci1_hose);
659 ft_fsl_pci_setup(blob, "pci1", &pcie2_hose);
662 ft_fsl_pci_setup(blob, "pci2", &pcie1_hose);
665 ft_fsl_pci_setup(blob, "pci3", &pcie3_hose);