2 * Copyright 2008-2010, 2011 Freescale Semiconductor, Inc.
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
26 #include <asm/processor.h>
28 #include <asm/cache.h>
29 #include <asm/immap_85xx.h>
30 #include <asm/fsl_pci.h>
31 #include <asm/fsl_ddr_sdram.h>
33 #include <asm/fsl_serdes.h>
37 #include <spd_sdram.h>
38 #include <fdt_support.h>
44 #include "../common/sgmii_riser.h"
46 int board_early_init_f (void)
49 volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
51 setbits_be32(&gur->pmuxcr,
52 (MPC85xx_PMUXCR_SDHC_CD |
53 MPC85xx_PMUXCR_SDHC_WP));
55 /* The MPC8536DS board insert the SDHC_WP pin for erratum NMG_eSDHC118,
56 * however, this erratum only applies to MPC8536 Rev1.0.
57 * So set SDHC_WP to active-low when use MPC8536 Rev1.1 and greater.*/
58 if ((((SVR_MAJ(get_svr()) & 0x7) == 0x1) &&
59 (SVR_MIN(get_svr()) >= 0x1))
60 || (SVR_MAJ(get_svr() & 0x7) > 0x1))
61 setbits_be32(&gur->gencfgr, MPC85xx_GENCFGR_SDHC_WP_INV);
69 u8 *pixis_base = (u8 *)PIXIS_BASE;
71 puts("Board: MPC8536DS ");
72 #ifdef CONFIG_PHYS_64BIT
73 puts("(36-bit addrmap) ");
76 printf ("Sys ID: 0x%02x, "
77 "Sys Ver: 0x%02x, FPGA Ver: 0x%02x, ",
78 in_8(pixis_base + PIXIS_ID), in_8(pixis_base + PIXIS_VER),
79 in_8(pixis_base + PIXIS_PVER));
81 vboot = in_8(pixis_base + PIXIS_VBOOT);
82 switch ((vboot & PIXIS_VBOOT_LBMAP) >> 5) {
83 case PIXIS_VBOOT_LBMAP_NOR0:
86 case PIXIS_VBOOT_LBMAP_NOR1:
89 case PIXIS_VBOOT_LBMAP_NOR2:
92 case PIXIS_VBOOT_LBMAP_NOR3:
95 case PIXIS_VBOOT_LBMAP_PJET:
98 case PIXIS_VBOOT_LBMAP_NAND:
106 #if !defined(CONFIG_SPD_EEPROM)
108 * Fixed sdram init -- doesn't use serial presence detect.
111 phys_size_t fixed_sdram (void)
113 volatile immap_t *immap = (immap_t *)CONFIG_SYS_IMMR;
114 volatile ccsr_ddr_t *ddr= &immap->im_ddr;
117 ddr->cs0_bnds = CONFIG_SYS_DDR_CS0_BNDS;
118 ddr->cs0_config = CONFIG_SYS_DDR_CS0_CONFIG;
120 ddr->timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
121 ddr->timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
122 ddr->timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
123 ddr->timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
124 ddr->sdram_mode = CONFIG_SYS_DDR_MODE_1;
125 ddr->sdram_mode_2 = CONFIG_SYS_DDR_MODE_2;
126 ddr->sdram_interval = CONFIG_SYS_DDR_INTERVAL;
127 ddr->sdram_data_init = CONFIG_SYS_DDR_DATA_INIT;
128 ddr->sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CTRL;
129 ddr->sdram_cfg_2 = CONFIG_SYS_DDR_CONTROL2;
131 #if defined (CONFIG_DDR_ECC)
132 ddr->err_int_en = CONFIG_SYS_DDR_ERR_INT_EN;
133 ddr->err_disable = CONFIG_SYS_DDR_ERR_DIS;
134 ddr->err_sbe = CONFIG_SYS_DDR_SBE;
140 ddr->sdram_cfg = CONFIG_SYS_DDR_CONTROL;
142 #if defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
144 debug("DDR - 1st controller: memory initializing\n");
146 * Poll until memory is initialized.
147 * 512 Meg at 400 might hit this 200 times or so.
149 while ((ddr->sdram_cfg_2 & (d_init << 4)) != 0) {
152 debug("DDR: memory initialized\n\n");
157 return 512 * 1024 * 1024;
163 static struct pci_controller pci1_hose;
167 void pci_init_board(void)
169 ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
170 struct fsl_pci_info pci_info;
171 u32 devdisr, pordevsr;
172 u32 porpllsr, pci_agent, pci_speed, pci_32, pci_arb, pci_clk_sel;
173 int first_free_busno;
175 first_free_busno = fsl_pcie_init_board(0);
178 devdisr = in_be32(&gur->devdisr);
179 pordevsr = in_be32(&gur->pordevsr);
180 porpllsr = in_be32(&gur->porpllsr);
182 pci_speed = 66666000;
184 pci_arb = pordevsr & MPC85xx_PORDEVSR_PCI1_ARB;
185 pci_clk_sel = porpllsr & MPC85xx_PORDEVSR_PCI1_SPD;
187 if (!(devdisr & MPC85xx_DEVDISR_PCI1)) {
188 SET_STD_PCI_INFO(pci_info, 1);
189 set_next_law(pci_info.mem_phys,
190 law_size_bits(pci_info.mem_size), pci_info.law);
191 set_next_law(pci_info.io_phys,
192 law_size_bits(pci_info.io_size), pci_info.law);
194 pci_agent = fsl_setup_hose(&pci1_hose, pci_info.regs);
195 printf("PCI: %d bit, %s MHz, %s, %s, %s (base address %lx)\n",
197 (pci_speed == 33333000) ? "33" :
198 (pci_speed == 66666000) ? "66" : "unknown",
199 pci_clk_sel ? "sync" : "async",
200 pci_agent ? "agent" : "host",
201 pci_arb ? "arbiter" : "external-arbiter",
204 first_free_busno = fsl_pci_init_port(&pci_info,
205 &pci1_hose, first_free_busno);
207 printf("PCI: disabled\n");
212 setbits_be32(&gur->devdisr, MPC85xx_DEVDISR_PCI1); /* disable */
217 int board_early_init_r(void)
219 const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
220 const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
223 * Remap Boot flash + PROMJET region to caching-inhibited
224 * so that flash can be erased properly.
227 /* Flush d-cache and invalidate i-cache of any FLASH data */
231 /* invalidate existing TLB entry for flash + promjet */
232 disable_tlb(flash_esel);
234 set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
235 MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, /* perms, wimge */
236 0, flash_esel, BOOKE_PAGESZ_256M, 1); /* ts, esel, tsize, iprot */
241 int board_eth_init(bd_t *bis)
243 #ifdef CONFIG_TSEC_ENET
244 struct fsl_pq_mdio_info mdio_info;
245 struct tsec_info_struct tsec_info[2];
249 SET_STD_TSEC_INFO(tsec_info[num], 1);
250 if (is_serdes_configured(SGMII_TSEC1)) {
251 puts("eTSEC1 is in sgmii mode.\n");
252 tsec_info[num].phyaddr = 0;
253 tsec_info[num].flags |= TSEC_SGMII;
258 SET_STD_TSEC_INFO(tsec_info[num], 3);
259 if (is_serdes_configured(SGMII_TSEC3)) {
260 puts("eTSEC3 is in sgmii mode.\n");
261 tsec_info[num].phyaddr = 1;
262 tsec_info[num].flags |= TSEC_SGMII;
268 printf("No TSECs initialized\n");
272 #ifdef CONFIG_FSL_SGMII_RISER
273 if (is_serdes_configured(SGMII_TSEC1) ||
274 is_serdes_configured(SGMII_TSEC3)) {
275 fsl_sgmii_riser_init(tsec_info, num);
279 mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR;
280 mdio_info.name = DEFAULT_MII_NAME;
281 fsl_pq_mdio_init(bis, &mdio_info);
283 tsec_eth_init(bis, tsec_info, num);
285 return pci_eth_init(bis);
288 #if defined(CONFIG_OF_BOARD_SETUP)
289 void ft_board_setup(void *blob, bd_t *bd)
291 ft_cpu_setup(blob, bd);
295 #ifdef CONFIG_FSL_SGMII_RISER
296 fsl_sgmii_riser_fdt_fixup(blob);