1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
14 #include <asm/fsl_mpc83xx_serdes.h>
15 #include <fdt_support.h>
16 #include <spd_sdram.h>
18 #include <fsl_esdhc.h>
20 DECLARE_GLOBAL_DATA_PTR;
22 #if defined(CONFIG_SYS_DRAM_TEST)
26 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
27 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
30 printf("Testing DRAM from 0x%08x to 0x%08x\n",
31 CONFIG_SYS_MEMTEST_START,
32 CONFIG_SYS_MEMTEST_END);
34 printf("DRAM test phase 1:\n");
35 for (p = pstart; p < pend; p++)
38 for (p = pstart; p < pend; p++) {
39 if (*p != 0xaaaaaaaa) {
40 printf("DRAM test fails at: %08x\n", (uint) p);
45 printf("DRAM test phase 2:\n");
46 for (p = pstart; p < pend; p++)
49 for (p = pstart; p < pend; p++) {
50 if (*p != 0x55555555) {
51 printf("DRAM test fails at: %08x\n", (uint) p);
56 printf("DRAM test passed.\n");
61 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
62 void ddr_enable_ecc(unsigned int dram_size);
64 int fixed_sdram(void);
68 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
71 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
74 #if defined(CONFIG_SPD_EEPROM)
77 msize = fixed_sdram();
80 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
81 /* Initialize DDR ECC byte */
82 ddr_enable_ecc(msize * 1024 * 1024);
84 /* return total bus DDR size(bytes) */
85 gd->ram_size = msize * 1024 * 1024;
90 #if !defined(CONFIG_SPD_EEPROM)
91 /*************************************************************************
92 * fixed sdram init -- doesn't use serial presence detect.
93 ************************************************************************/
96 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
97 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
98 u32 msize_log2 = __ilog2(msize);
100 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
101 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
103 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
106 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
109 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
110 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
113 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
114 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
115 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
116 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
117 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
118 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
119 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
120 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
121 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
125 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
127 return CONFIG_SYS_DDR_SIZE;
129 #endif /*!CONFIG_SYS_SPD_EEPROM */
133 puts("Board: Freescale MPC837xERDB\n");
137 int board_early_init_f(void)
139 #ifdef CONFIG_FSL_SERDES
140 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
141 u32 spridr = in_be32(&immr->sysconf.spridr);
143 /* we check only part num, and don't look for CPU revisions */
144 switch (PARTID_NO_E(spridr)) {
146 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
147 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
148 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
149 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
152 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
153 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
156 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
157 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
158 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
159 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
162 printf("serdes not configured: unknown CPU part number: "
163 "%04x\n", spridr >> 16);
166 #endif /* CONFIG_FSL_SERDES */
170 #ifdef CONFIG_FSL_ESDHC
171 int board_mmc_init(bd_t *bd)
173 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
174 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
175 int esdhc_hwconfig_enabled = 0;
177 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
178 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
180 if (esdhc_hwconfig_enabled == 0)
183 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
184 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
186 return fsl_esdhc_mmc_init(bd);
191 * Miscellaneous late-boot configurations
193 * If a VSC7385 microcode image is present, then upload it.
195 int misc_init_r(void)
199 #ifdef CONFIG_VSC7385_IMAGE
200 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
201 CONFIG_VSC7385_IMAGE_SIZE)) {
202 puts("Failure uploading VSC7385 microcode.\n");
210 #if defined(CONFIG_OF_BOARD_SETUP)
212 int ft_board_setup(void *blob, bd_t *bd)
215 ft_pci_setup(blob, bd);
217 ft_cpu_setup(blob, bd);
218 fsl_fdt_fixup_dr_usb(blob, bd);
219 fdt_fixup_esdhc(blob, bd);
223 #endif /* CONFIG_OF_BOARD_SETUP */