1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Kevin Lam <kevin.lam@freescale.com>
5 * Joe D'Abbraccio <joe.d'abbraccio@freescale.com>
12 #include <asm/fsl_mpc83xx_serdes.h>
13 #include <fdt_support.h>
14 #include <spd_sdram.h>
16 #include <fsl_esdhc.h>
18 DECLARE_GLOBAL_DATA_PTR;
20 #if defined(CONFIG_SYS_DRAM_TEST)
24 uint *pstart = (uint *) CONFIG_SYS_MEMTEST_START;
25 uint *pend = (uint *) CONFIG_SYS_MEMTEST_END;
28 printf("Testing DRAM from 0x%08x to 0x%08x\n",
29 CONFIG_SYS_MEMTEST_START,
30 CONFIG_SYS_MEMTEST_END);
32 printf("DRAM test phase 1:\n");
33 for (p = pstart; p < pend; p++)
36 for (p = pstart; p < pend; p++) {
37 if (*p != 0xaaaaaaaa) {
38 printf("DRAM test fails at: %08x\n", (uint) p);
43 printf("DRAM test phase 2:\n");
44 for (p = pstart; p < pend; p++)
47 for (p = pstart; p < pend; p++) {
48 if (*p != 0x55555555) {
49 printf("DRAM test fails at: %08x\n", (uint) p);
54 printf("DRAM test passed.\n");
59 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
60 void ddr_enable_ecc(unsigned int dram_size);
62 int fixed_sdram(void);
66 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
69 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
72 #if defined(CONFIG_SPD_EEPROM)
75 msize = fixed_sdram();
78 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
79 /* Initialize DDR ECC byte */
80 ddr_enable_ecc(msize * 1024 * 1024);
82 /* return total bus DDR size(bytes) */
83 gd->ram_size = msize * 1024 * 1024;
88 #if !defined(CONFIG_SPD_EEPROM)
89 /*************************************************************************
90 * fixed sdram init -- doesn't use serial presence detect.
91 ************************************************************************/
94 immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
95 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
96 u32 msize_log2 = __ilog2(msize);
98 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
99 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
101 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
104 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
107 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
108 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
111 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
112 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
113 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
114 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
115 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
116 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
117 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
118 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
119 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
123 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
125 return CONFIG_SYS_DDR_SIZE;
127 #endif /*!CONFIG_SYS_SPD_EEPROM */
131 puts("Board: Freescale MPC837xERDB\n");
135 int board_early_init_f(void)
137 #ifdef CONFIG_FSL_SERDES
138 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
139 u32 spridr = in_be32(&immr->sysconf.spridr);
141 /* we check only part num, and don't look for CPU revisions */
142 switch (PARTID_NO_E(spridr)) {
144 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
145 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
146 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
147 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
150 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_PEX,
151 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
154 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_SATA,
155 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
156 fsl_setup_serdes(CONFIG_FSL_SERDES2, FSL_SERDES_PROTO_SATA,
157 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
160 printf("serdes not configured: unknown CPU part number: "
161 "%04x\n", spridr >> 16);
164 #endif /* CONFIG_FSL_SERDES */
168 #ifdef CONFIG_FSL_ESDHC
169 int board_mmc_init(bd_t *bd)
171 struct immap __iomem *im = (struct immap __iomem *)CONFIG_SYS_IMMR;
172 char buffer[HWCONFIG_BUFFER_SIZE] = {0};
173 int esdhc_hwconfig_enabled = 0;
175 if (env_get_f("hwconfig", buffer, sizeof(buffer)) > 0)
176 esdhc_hwconfig_enabled = hwconfig_f("esdhc", buffer);
178 if (esdhc_hwconfig_enabled == 0)
181 clrsetbits_be32(&im->sysconf.sicrl, SICRL_USB_B, SICRL_USB_B_SD);
182 clrsetbits_be32(&im->sysconf.sicrh, SICRH_SPI, SICRH_SPI_SD);
184 return fsl_esdhc_mmc_init(bd);
189 * Miscellaneous late-boot configurations
191 * If a VSC7385 microcode image is present, then upload it.
193 int misc_init_r(void)
197 #ifdef CONFIG_VSC7385_IMAGE
198 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
199 CONFIG_VSC7385_IMAGE_SIZE)) {
200 puts("Failure uploading VSC7385 microcode.\n");
208 #if defined(CONFIG_OF_BOARD_SETUP)
210 int ft_board_setup(void *blob, bd_t *bd)
213 ft_pci_setup(blob, bd);
215 ft_cpu_setup(blob, bd);
216 fsl_fdt_fixup_dr_usb(blob, bd);
217 fdt_fixup_esdhc(blob, bd);
221 #endif /* CONFIG_OF_BOARD_SETUP */