2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * CREDITS: Kim Phillips contribute to LIBFDT code
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
16 #if defined(CONFIG_SPD_EEPROM)
17 #include <spd_sdram.h>
19 #if defined(CONFIG_OF_FLAT_TREE)
21 #elif defined(CONFIG_OF_LIBFDT)
24 #if defined(CONFIG_PQ_MDS_PIB)
25 #include "../common/pq-mds-pib.h"
28 int board_early_init_f(void)
30 u8 *bcsr = (u8 *)CFG_BCSR;
32 /* Enable flash write */
34 /* Clear all of the interrupt of BCSR */
40 int board_early_init_r(void)
42 #ifdef CONFIG_PQ_MDS_PIB
48 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
49 extern void ddr_enable_ecc(unsigned int dram_size);
51 int fixed_sdram(void);
53 long int initdram(int board_type)
55 volatile immap_t *im = (immap_t *) CFG_IMMR;
58 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
61 #if defined(CONFIG_SPD_EEPROM)
64 msize = fixed_sdram();
67 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRC)
68 /* Initialize DDR ECC byte */
69 ddr_enable_ecc(msize * 1024 * 1024);
72 /* return total bus DDR size(bytes) */
73 return (msize * 1024 * 1024);
76 #if !defined(CONFIG_SPD_EEPROM)
77 /*************************************************************************
78 * fixed sdram init -- doesn't use serial presence detect.
79 ************************************************************************/
82 volatile immap_t *im = (immap_t *) CFG_IMMR;
83 u32 msize = CFG_DDR_SIZE * 1024 * 1024;
84 u32 msize_log2 = __ilog2(msize);
86 im->sysconf.ddrlaw[0].bar = CFG_DDR_SDRAM_BASE >> 12;
87 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
89 #if (CFG_DDR_SIZE != 512)
90 #warning Currenly any ddr size other than 512 is not supported
92 im->sysconf.ddrcdr = CFG_DDRCDR_VALUE;
95 im->ddr.sdram_clk_cntl = CFG_DDR_SDRAM_CLK_CNTL;
98 im->ddr.csbnds[0].csbnds = CFG_DDR_CS0_BNDS;
99 im->ddr.cs_config[0] = CFG_DDR_CS0_CONFIG;
102 im->ddr.timing_cfg_0 = CFG_DDR_TIMING_0;
103 im->ddr.timing_cfg_1 = CFG_DDR_TIMING_1;
104 im->ddr.timing_cfg_2 = CFG_DDR_TIMING_2;
105 im->ddr.timing_cfg_3 = CFG_DDR_TIMING_3;
106 im->ddr.sdram_cfg = CFG_DDR_SDRAM_CFG;
107 im->ddr.sdram_cfg2 = CFG_DDR_SDRAM_CFG2;
108 im->ddr.sdram_mode = CFG_DDR_MODE;
109 im->ddr.sdram_mode2 = CFG_DDR_MODE2;
110 im->ddr.sdram_interval = CFG_DDR_INTERVAL;
111 __asm__ __volatile__("sync");
114 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
118 #endif /*!CFG_SPD_EEPROM */
122 puts("Board: Freescale MPC837xEMDS\n");
126 #if defined(CONFIG_OF_BOARD_SETUP)
127 void ft_board_setup(void *blob, bd_t *bd)
129 #if defined(CONFIG_OF_FLAT_TREE)
133 p = ft_get_prop(blob, "/memory/reg", &len);
135 *p++ = cpu_to_be32(bd->bi_memstart);
136 *p = cpu_to_be32(bd->bi_memsize);
139 ft_cpu_setup(blob, bd);
141 ft_pci_setup(blob, bd);
144 #endif /* CONFIG_OF_BOARD_SETUP */