2 * Copyright (C) 2006,2010-2011 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * SPDX-License-Identifier: GPL-2.0+
15 #if defined(CONFIG_PCI)
18 #include <spd_sdram.h>
22 #if defined(CONFIG_OF_LIBFDT)
26 #include <fdt_support.h>
27 #if defined(CONFIG_PQ_MDS_PIB)
28 #include "../common/pq-mds-pib.h"
30 #include "../../../drivers/qe/uec.h"
32 const qe_iop_conf_t qe_iop_conf_tab[] = {
34 {0, 3, 1, 0, 1}, /* TxD0 */
35 {0, 4, 1, 0, 1}, /* TxD1 */
36 {0, 5, 1, 0, 1}, /* TxD2 */
37 {0, 6, 1, 0, 1}, /* TxD3 */
38 {1, 6, 1, 0, 3}, /* TxD4 */
39 {1, 7, 1, 0, 1}, /* TxD5 */
40 {1, 9, 1, 0, 2}, /* TxD6 */
41 {1, 10, 1, 0, 2}, /* TxD7 */
42 {0, 9, 2, 0, 1}, /* RxD0 */
43 {0, 10, 2, 0, 1}, /* RxD1 */
44 {0, 11, 2, 0, 1}, /* RxD2 */
45 {0, 12, 2, 0, 1}, /* RxD3 */
46 {0, 13, 2, 0, 1}, /* RxD4 */
47 {1, 1, 2, 0, 2}, /* RxD5 */
48 {1, 0, 2, 0, 2}, /* RxD6 */
49 {1, 4, 2, 0, 2}, /* RxD7 */
50 {0, 7, 1, 0, 1}, /* TX_EN */
51 {0, 8, 1, 0, 1}, /* TX_ER */
52 {0, 15, 2, 0, 1}, /* RX_DV */
53 {0, 16, 2, 0, 1}, /* RX_ER */
54 {0, 0, 2, 0, 1}, /* RX_CLK */
55 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
56 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
58 {0, 17, 1, 0, 1}, /* TxD0 */
59 {0, 18, 1, 0, 1}, /* TxD1 */
60 {0, 19, 1, 0, 1}, /* TxD2 */
61 {0, 20, 1, 0, 1}, /* TxD3 */
62 {1, 2, 1, 0, 1}, /* TxD4 */
63 {1, 3, 1, 0, 2}, /* TxD5 */
64 {1, 5, 1, 0, 3}, /* TxD6 */
65 {1, 8, 1, 0, 3}, /* TxD7 */
66 {0, 23, 2, 0, 1}, /* RxD0 */
67 {0, 24, 2, 0, 1}, /* RxD1 */
68 {0, 25, 2, 0, 1}, /* RxD2 */
69 {0, 26, 2, 0, 1}, /* RxD3 */
70 {0, 27, 2, 0, 1}, /* RxD4 */
71 {1, 12, 2, 0, 2}, /* RxD5 */
72 {1, 13, 2, 0, 3}, /* RxD6 */
73 {1, 11, 2, 0, 2}, /* RxD7 */
74 {0, 21, 1, 0, 1}, /* TX_EN */
75 {0, 22, 1, 0, 1}, /* TX_ER */
76 {0, 29, 2, 0, 1}, /* RX_DV */
77 {0, 30, 2, 0, 1}, /* RX_ER */
78 {0, 31, 2, 0, 1}, /* RX_CLK */
79 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
80 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
82 {0, 1, 3, 0, 2}, /* MDIO */
83 {0, 2, 1, 0, 1}, /* MDC */
85 {5, 0, 1, 0, 2}, /* UART2_SOUT */
86 {5, 1, 2, 0, 3}, /* UART2_CTS */
87 {5, 2, 1, 0, 1}, /* UART2_RTS */
88 {5, 3, 2, 0, 2}, /* UART2_SIN */
90 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
93 /* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
94 static int board_handle_erratum2(void)
96 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
98 return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
99 REVID_MINOR(immr->sysconf.spridr) == 1;
102 int board_early_init_f(void)
104 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
105 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
107 /* Enable flash write */
110 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
111 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
114 /* Enable second UART */
117 if (board_handle_erratum2()) {
118 void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
121 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
122 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
124 setbits_be32(immap, 0x0c003000);
127 * IMMR + 0x14AC[20:27] = 10101010
128 * (data delay for both UCC's)
130 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
135 int board_early_init_r(void)
138 #ifdef CONFIG_PQ_MDS_PIB
142 * BAT6 is used for SDRAM when DDR size is 512MB or larger than 256MB
143 * So re-setup PCI MEM space used BAT5 after relocated to DDR
145 gd = (gd_t *)(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
146 if (gd->ram_size > CONFIG_MAX_MEM_MAPPED) {
147 write_bat(DBAT5, CONFIG_SYS_DBAT6U, CONFIG_SYS_DBAT6L);
148 write_bat(IBAT5, CONFIG_SYS_IBAT6U, CONFIG_SYS_IBAT6L);
154 #ifdef CONFIG_UEC_ETH
155 static uec_info_t uec_info[] = {
156 #ifdef CONFIG_UEC_ETH1
159 #ifdef CONFIG_UEC_ETH2
164 int board_eth_init(bd_t *bd)
166 if (board_handle_erratum2()) {
169 for (i = 0; i < ARRAY_SIZE(uec_info); i++) {
170 uec_info[i].enet_interface_type =
171 PHY_INTERFACE_MODE_RGMII_RXID;
172 uec_info[i].speed = SPEED_1000;
175 return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
177 #endif /* CONFIG_UEC_ETH */
179 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
180 extern void ddr_enable_ecc(unsigned int dram_size);
182 int fixed_sdram(void);
183 static int sdram_init(unsigned int base);
185 phys_size_t initdram(int board_type)
187 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
191 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
194 /* DDR SDRAM - Main SODIMM */
195 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
196 #if defined(CONFIG_SPD_EEPROM)
199 msize = fixed_sdram();
202 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
204 * Initialize DDR ECC byte
206 ddr_enable_ecc(msize * 1024 * 1024);
209 * Initialize SDRAM if it is on local bus.
211 lbc_sdram_size = sdram_init(msize * 1024 * 1024);
213 msize = lbc_sdram_size;
215 /* return total bus SDRAM size(bytes) -- DDR */
216 return (msize * 1024 * 1024);
219 #if !defined(CONFIG_SPD_EEPROM)
220 /*************************************************************************
221 * fixed sdram init -- doesn't use serial presence detect.
222 ************************************************************************/
223 int fixed_sdram(void)
225 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
226 u32 msize = CONFIG_SYS_DDR_SIZE;
227 u32 ddr_size = msize << 20;
228 u32 ddr_size_log2 = __ilog2(ddr_size);
229 u32 half_ddr_size = ddr_size >> 1;
231 im->sysconf.ddrlaw[0].bar =
232 CONFIG_SYS_DDR_SDRAM_BASE & 0xfffff000;
233 im->sysconf.ddrlaw[0].ar =
234 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
235 #if (CONFIG_SYS_DDR_SIZE != 256)
236 #warning Currenly any ddr size other than 256 is not supported
239 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
240 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
241 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
242 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
243 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
244 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
245 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
246 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
247 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
248 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
249 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
250 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
253 #if ((CONFIG_SYS_DDR_SDRAM_BASE & 0x00FFFFFF) != 0)
254 #warning Chip select bounds is only configurable in 16MB increments
256 im->ddr.csbnds[0].csbnds =
257 ((CONFIG_SYS_DDR_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
258 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size - 1) >>
259 CSBNDS_EA_SHIFT) & CSBNDS_EA);
260 im->ddr.csbnds[1].csbnds =
261 (((CONFIG_SYS_DDR_SDRAM_BASE + half_ddr_size) >>
262 CSBNDS_SA_SHIFT) & CSBNDS_SA) |
263 (((CONFIG_SYS_DDR_SDRAM_BASE + ddr_size - 1) >>
264 CSBNDS_EA_SHIFT) & CSBNDS_EA);
266 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
267 im->ddr.cs_config[1] = CONFIG_SYS_DDR_CS1_CONFIG;
269 im->ddr.cs_config[2] = 0;
270 im->ddr.cs_config[3] = 0;
272 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
273 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
274 im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
276 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
277 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
280 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
284 #endif /*!CONFIG_SYS_SPD_EEPROM */
288 puts("Board: Freescale MPC8360EMDS\n");
293 * if MPC8360EMDS is soldered with SDRAM
295 #ifdef CONFIG_SYS_LB_SDRAM
297 * Initialize SDRAM memory on the Local Bus.
300 static int sdram_init(unsigned int base)
302 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
303 fsl_lbc_t *lbc = LBC_BASE_ADDR;
304 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
305 int rem = base % sdram_size;
308 /* window base address should be aligned to the window size */
310 base = base - rem + sdram_size;
313 * Setup BAT6 for SDRAM when DDR size is 512MB or larger than 256MB
314 * After relocated to DDR, reuse BAT5 for PCI MEM space
316 if (base > CONFIG_MAX_MEM_MAPPED) {
317 unsigned long batl = base | BATL_PP_10 | BATL_MEMCOHERENCE;
318 unsigned long batu = base | BATU_BL_64M | BATU_VS | BATU_VP;
320 /* Setup the BAT6 for SDRAM */
321 write_bat(DBAT6, batu, batl);
322 write_bat(IBAT6, batu, batl);
325 sdram_addr = (uint *)base;
327 * Setup SDRAM Base and Option Registers
329 set_lbc_br(2, base | CONFIG_SYS_BR2);
330 set_lbc_or(2, CONFIG_SYS_OR2);
331 immap->sysconf.lblaw[2].bar = base;
332 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
334 /*setup mtrpt, lsrt and lbcr for LB bus */
335 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
336 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
337 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
341 * Configure the SDRAM controller Machine Mode Register.
343 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
344 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
350 * We need do 8 times auto refresh operation.
352 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
354 *sdram_addr = 0xff; /* 1 times */
356 *sdram_addr = 0xff; /* 2 times */
358 *sdram_addr = 0xff; /* 3 times */
360 *sdram_addr = 0xff; /* 4 times */
362 *sdram_addr = 0xff; /* 5 times */
364 *sdram_addr = 0xff; /* 6 times */
366 *sdram_addr = 0xff; /* 7 times */
368 *sdram_addr = 0xff; /* 8 times */
371 /* Mode register write operation */
372 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
374 *(sdram_addr + 0xcc) = 0xff;
377 /* Normal operation */
378 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
384 * In non-aligned case we don't [normally] use that memory because
389 return CONFIG_SYS_LBC_SDRAM_SIZE;
392 static int sdram_init(unsigned int base) { return 0; }
395 #if defined(CONFIG_OF_BOARD_SETUP)
396 static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
398 if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
401 do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
402 "peripheral", sizeof("peripheral"), 1);
405 int ft_board_setup(void *blob, bd_t *bd)
407 ft_cpu_setup(blob, bd);
409 ft_pci_setup(blob, bd);
411 ft_board_fixup_qe_usb(blob, bd);
413 * mpc8360ea pb mds errata 2: RGMII timing
414 * if on mpc8360ea rev. 2.1,
415 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
417 if (board_handle_erratum2()) {
422 nodeoffset = fdt_path_offset(blob, "/aliases");
423 if (nodeoffset >= 0) {
424 #if defined(CONFIG_HAS_ETH0)
425 /* fixup UCC 1 if using rgmii-id mode */
426 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
428 path = fdt_path_offset(blob, prop);
429 prop = fdt_getprop(blob, path,
430 "phy-connection-type", 0);
431 if (prop && (strcmp(prop, "rgmii-id") == 0))
432 fdt_fixup_phy_connection(blob, path,
433 PHY_INTERFACE_MODE_RGMII_RXID);
436 #if defined(CONFIG_HAS_ETH1)
437 /* fixup UCC 2 if using rgmii-id mode */
438 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
440 path = fdt_path_offset(blob, prop);
441 prop = fdt_getprop(blob, path,
442 "phy-connection-type", 0);
443 if (prop && (strcmp(prop, "rgmii-id") == 0))
444 fdt_fixup_phy_connection(blob, path,
445 PHY_INTERFACE_MODE_RGMII_RXID);