2 * Copyright (C) 2006,2010 Freescale Semiconductor, Inc.
3 * Dave Liu <daveliu@freescale.com>
5 * See file CREDITS for list of people who contributed to this
8 * This program is free software; you can redistribute it and/or
9 * modify it under the terms of the GNU General Public License as
10 * published by the Free Software Foundation; either version 2 of
11 * the License, or (at your option) any later version.
20 #if defined(CONFIG_PCI)
23 #include <spd_sdram.h>
26 #include <asm/fsl_enet.h>
27 #if defined(CONFIG_OF_LIBFDT)
31 #include <fdt_support.h>
32 #if defined(CONFIG_PQ_MDS_PIB)
33 #include "../common/pq-mds-pib.h"
35 #include "../../../drivers/qe/uec.h"
37 const qe_iop_conf_t qe_iop_conf_tab[] = {
39 {0, 3, 1, 0, 1}, /* TxD0 */
40 {0, 4, 1, 0, 1}, /* TxD1 */
41 {0, 5, 1, 0, 1}, /* TxD2 */
42 {0, 6, 1, 0, 1}, /* TxD3 */
43 {1, 6, 1, 0, 3}, /* TxD4 */
44 {1, 7, 1, 0, 1}, /* TxD5 */
45 {1, 9, 1, 0, 2}, /* TxD6 */
46 {1, 10, 1, 0, 2}, /* TxD7 */
47 {0, 9, 2, 0, 1}, /* RxD0 */
48 {0, 10, 2, 0, 1}, /* RxD1 */
49 {0, 11, 2, 0, 1}, /* RxD2 */
50 {0, 12, 2, 0, 1}, /* RxD3 */
51 {0, 13, 2, 0, 1}, /* RxD4 */
52 {1, 1, 2, 0, 2}, /* RxD5 */
53 {1, 0, 2, 0, 2}, /* RxD6 */
54 {1, 4, 2, 0, 2}, /* RxD7 */
55 {0, 7, 1, 0, 1}, /* TX_EN */
56 {0, 8, 1, 0, 1}, /* TX_ER */
57 {0, 15, 2, 0, 1}, /* RX_DV */
58 {0, 16, 2, 0, 1}, /* RX_ER */
59 {0, 0, 2, 0, 1}, /* RX_CLK */
60 {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */
61 {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */
63 {0, 17, 1, 0, 1}, /* TxD0 */
64 {0, 18, 1, 0, 1}, /* TxD1 */
65 {0, 19, 1, 0, 1}, /* TxD2 */
66 {0, 20, 1, 0, 1}, /* TxD3 */
67 {1, 2, 1, 0, 1}, /* TxD4 */
68 {1, 3, 1, 0, 2}, /* TxD5 */
69 {1, 5, 1, 0, 3}, /* TxD6 */
70 {1, 8, 1, 0, 3}, /* TxD7 */
71 {0, 23, 2, 0, 1}, /* RxD0 */
72 {0, 24, 2, 0, 1}, /* RxD1 */
73 {0, 25, 2, 0, 1}, /* RxD2 */
74 {0, 26, 2, 0, 1}, /* RxD3 */
75 {0, 27, 2, 0, 1}, /* RxD4 */
76 {1, 12, 2, 0, 2}, /* RxD5 */
77 {1, 13, 2, 0, 3}, /* RxD6 */
78 {1, 11, 2, 0, 2}, /* RxD7 */
79 {0, 21, 1, 0, 1}, /* TX_EN */
80 {0, 22, 1, 0, 1}, /* TX_ER */
81 {0, 29, 2, 0, 1}, /* RX_DV */
82 {0, 30, 2, 0, 1}, /* RX_ER */
83 {0, 31, 2, 0, 1}, /* RX_CLK */
84 {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */
85 {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */
87 {0, 1, 3, 0, 2}, /* MDIO */
88 {0, 2, 1, 0, 1}, /* MDC */
90 {5, 0, 1, 0, 2}, /* UART2_SOUT */
91 {5, 1, 2, 0, 3}, /* UART2_CTS */
92 {5, 2, 1, 0, 1}, /* UART2_RTS */
93 {5, 3, 2, 0, 2}, /* UART2_SIN */
95 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
98 /* Handle "mpc8360ea rev.2.1 erratum 2: RGMII Timing"? */
99 static int board_handle_erratum2(void)
101 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
103 return REVID_MAJOR(immr->sysconf.spridr) == 2 &&
104 REVID_MINOR(immr->sysconf.spridr) == 1;
107 int board_early_init_f(void)
109 const immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
110 u8 *bcsr = (u8 *)CONFIG_SYS_BCSR;
112 /* Enable flash write */
115 /* Disable G1TXCLK, G2TXCLK h/w buffers (rev.2.x h/w bug workaround) */
116 if (REVID_MAJOR(immr->sysconf.spridr) == 2)
119 /* Enable second UART */
122 if (board_handle_erratum2()) {
123 void *immap = (immap_t *)(CONFIG_SYS_IMMR + 0x14a8);
126 * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
127 * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
129 setbits_be32(immap, 0x0c003000);
132 * IMMR + 0x14AC[20:27] = 10101010
133 * (data delay for both UCC's)
135 clrsetbits_be32(immap + 4, 0xff0, 0xaa0);
140 int board_early_init_r(void)
142 #ifdef CONFIG_PQ_MDS_PIB
148 #ifdef CONFIG_UEC_ETH
149 static uec_info_t uec_info[] = {
150 #ifdef CONFIG_UEC_ETH1
153 #ifdef CONFIG_UEC_ETH2
158 int board_eth_init(bd_t *bd)
160 if (board_handle_erratum2()) {
163 for (i = 0; i < ARRAY_SIZE(uec_info); i++)
164 uec_info[i].enet_interface_type =
165 PHY_INTERFACE_MODE_RGMII_RXID;
166 uec_info[i].speed = SPEED_1000;
168 return uec_eth_init(bd, uec_info, ARRAY_SIZE(uec_info));
170 #endif /* CONFIG_UEC_ETH */
172 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
173 extern void ddr_enable_ecc(unsigned int dram_size);
175 int fixed_sdram(void);
176 static int sdram_init(unsigned int base);
178 phys_size_t initdram(int board_type)
180 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
184 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
187 /* DDR SDRAM - Main SODIMM */
188 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_DDR_BASE & LAWBAR_BAR;
189 #if defined(CONFIG_SPD_EEPROM)
192 msize = fixed_sdram();
195 #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
197 * Initialize DDR ECC byte
199 ddr_enable_ecc(msize * 1024 * 1024);
202 * Initialize SDRAM if it is on local bus.
204 lbc_sdram_size = sdram_init(msize * 1024 * 1024);
206 msize = lbc_sdram_size;
208 /* return total bus SDRAM size(bytes) -- DDR */
209 return (msize * 1024 * 1024);
212 #if !defined(CONFIG_SPD_EEPROM)
213 /*************************************************************************
214 * fixed sdram init -- doesn't use serial presence detect.
215 ************************************************************************/
216 int fixed_sdram(void)
218 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
223 msize = CONFIG_SYS_DDR_SIZE;
224 for (ddr_size = msize << 20, ddr_size_log2 = 0;
225 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
230 im->sysconf.ddrlaw[0].ar =
231 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
232 #if (CONFIG_SYS_DDR_SIZE != 256)
233 #warning Currenly any ddr size other than 256 is not supported
236 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
237 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
238 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
239 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
240 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
241 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
242 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
243 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
244 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
245 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
246 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
247 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
249 im->ddr.csbnds[0].csbnds = 0x00000007;
250 im->ddr.csbnds[1].csbnds = 0x0008000f;
252 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CONFIG;
253 im->ddr.cs_config[1] = CONFIG_SYS_DDR_CONFIG;
255 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
256 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
257 im->ddr.sdram_cfg = CONFIG_SYS_DDR_CONTROL;
259 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
260 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
263 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
267 #endif /*!CONFIG_SYS_SPD_EEPROM */
271 puts("Board: Freescale MPC8360EMDS\n");
276 * if MPC8360EMDS is soldered with SDRAM
278 #ifdef CONFIG_SYS_LB_SDRAM
280 * Initialize SDRAM memory on the Local Bus.
283 static int sdram_init(unsigned int base)
285 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
286 fsl_lbc_t *lbc = LBC_BASE_ADDR;
287 const int sdram_size = CONFIG_SYS_LBC_SDRAM_SIZE * 1024 * 1024;
288 int rem = base % sdram_size;
291 /* window base address should be aligned to the window size */
293 base = base - rem + sdram_size;
295 sdram_addr = (uint *)base;
297 * Setup SDRAM Base and Option Registers
299 set_lbc_br(2, base | CONFIG_SYS_BR2);
300 set_lbc_or(2, CONFIG_SYS_OR2);
301 immap->sysconf.lblaw[2].bar = base;
302 immap->sysconf.lblaw[2].ar = CONFIG_SYS_LBLAWAR2;
304 /*setup mtrpt, lsrt and lbcr for LB bus */
305 lbc->lbcr = CONFIG_SYS_LBC_LBCR;
306 lbc->mrtpr = CONFIG_SYS_LBC_MRTPR;
307 lbc->lsrt = CONFIG_SYS_LBC_LSRT;
311 * Configure the SDRAM controller Machine Mode Register.
313 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; /* Normal Operation */
314 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; /* Precharge All Banks */
320 * We need do 8 times auto refresh operation.
322 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2;
324 *sdram_addr = 0xff; /* 1 times */
326 *sdram_addr = 0xff; /* 2 times */
328 *sdram_addr = 0xff; /* 3 times */
330 *sdram_addr = 0xff; /* 4 times */
332 *sdram_addr = 0xff; /* 5 times */
334 *sdram_addr = 0xff; /* 6 times */
336 *sdram_addr = 0xff; /* 7 times */
338 *sdram_addr = 0xff; /* 8 times */
341 /* Mode register write operation */
342 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4;
344 *(sdram_addr + 0xcc) = 0xff;
347 /* Normal operation */
348 lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5 | 0x40000000;
354 * In non-aligned case we don't [normally] use that memory because
359 return CONFIG_SYS_LBC_SDRAM_SIZE;
362 static int sdram_init(unsigned int base) { return 0; }
365 #if defined(CONFIG_OF_BOARD_SETUP)
366 static void ft_board_fixup_qe_usb(void *blob, bd_t *bd)
368 if (!hwconfig_subarg_cmp("qe_usb", "mode", "peripheral"))
371 do_fixup_by_compat(blob, "fsl,mpc8323-qe-usb", "mode",
372 "peripheral", sizeof("peripheral"), 1);
375 void ft_board_setup(void *blob, bd_t *bd)
377 ft_cpu_setup(blob, bd);
379 ft_pci_setup(blob, bd);
381 ft_board_fixup_qe_usb(blob, bd);
383 * mpc8360ea pb mds errata 2: RGMII timing
384 * if on mpc8360ea rev. 2.1,
385 * change both ucc phy-connection-types from rgmii-id to rgmii-rxid
387 if (board_handle_erratum2()) {
392 nodeoffset = fdt_path_offset(blob, "/aliases");
393 if (nodeoffset >= 0) {
394 #if defined(CONFIG_HAS_ETH0)
395 /* fixup UCC 1 if using rgmii-id mode */
396 prop = fdt_getprop(blob, nodeoffset, "ethernet0", NULL);
398 path = fdt_path_offset(blob, prop);
399 prop = fdt_getprop(blob, path,
400 "phy-connection-type", 0);
401 if (prop && (strcmp(prop, "rgmii-id") == 0))
402 fdt_fixup_phy_connection(blob, path,
403 PHY_INTERFACE_MODE_RGMII_RXID);
406 #if defined(CONFIG_HAS_ETH1)
407 /* fixup UCC 2 if using rgmii-id mode */
408 prop = fdt_getprop(blob, nodeoffset, "ethernet1", NULL);
410 path = fdt_path_offset(blob, prop);
411 prop = fdt_getprop(blob, path,
412 "phy-connection-type", 0);
413 if (prop && (strcmp(prop, "rgmii-id") == 0))
414 fdt_fixup_phy_connection(blob, path,
415 PHY_INTERFACE_MODE_RGMII_RXID);