1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) Freescale Semiconductor, Inc. 2006.
13 #include <asm/mpc8349_pci.h>
16 #include <spd_sdram.h>
18 #if defined(CONFIG_OF_LIBFDT)
19 #include <linux/libfdt.h>
22 #include "../../../arch/powerpc/cpu/mpc83xx/hrcw/hrcw.h"
23 #include "../../../arch/powerpc/cpu/mpc83xx/elbc/elbc.h"
25 DECLARE_GLOBAL_DATA_PTR;
27 #ifndef CONFIG_SPD_EEPROM
28 /*************************************************************************
29 * fixed sdram init -- doesn't use serial presence detect.
30 ************************************************************************/
33 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
34 /* The size of RAM, in bytes */
35 u32 ddr_size = CONFIG_SYS_DDR_SIZE << 20;
36 u32 ddr_size_log2 = __ilog2(ddr_size);
38 im->sysconf.ddrlaw[0].ar =
39 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
40 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
42 #if ((CONFIG_SYS_SDRAM_BASE & 0x00FFFFFF) != 0)
43 #warning Chip select bounds is only configurable in 16MB increments
45 im->ddr.csbnds[0].csbnds =
46 ((CONFIG_SYS_SDRAM_BASE >> CSBNDS_SA_SHIFT) & CSBNDS_SA) |
47 (((CONFIG_SYS_SDRAM_BASE + ddr_size - 1) >>
48 CSBNDS_EA_SHIFT) & CSBNDS_EA);
49 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
51 /* Only one CS for DDR */
52 im->ddr.cs_config[1] = 0;
53 im->ddr.cs_config[2] = 0;
54 im->ddr.cs_config[3] = 0;
56 debug("cs0_bnds = 0x%08x\n", im->ddr.csbnds[0].csbnds);
57 debug("cs0_config = 0x%08x\n", im->ddr.cs_config[0]);
59 debug("DDR:bar=0x%08x\n", im->sysconf.ddrlaw[0].bar);
60 debug("DDR:ar=0x%08x\n", im->sysconf.ddrlaw[0].ar);
62 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
63 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;/* Was "2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT" */
64 im->ddr.sdram_cfg = SDRAM_CFG_SREN | SDRAM_CFG_SDRAM_TYPE_DDR1;
66 (0x0000 << SDRAM_MODE_ESD_SHIFT) | (0x0032 << SDRAM_MODE_SD_SHIFT);
67 im->ddr.sdram_interval =
68 (0x0410 << SDRAM_INTERVAL_REFINT_SHIFT) | (0x0100 <<
69 SDRAM_INTERVAL_BSTOPRE_SHIFT);
70 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
74 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
76 debug("DDR:timing_cfg_1=0x%08x\n", im->ddr.timing_cfg_1);
77 debug("DDR:timing_cfg_2=0x%08x\n", im->ddr.timing_cfg_2);
78 debug("DDR:sdram_mode=0x%08x\n", im->ddr.sdram_mode);
79 debug("DDR:sdram_interval=0x%08x\n", im->ddr.sdram_interval);
80 debug("DDR:sdram_cfg=0x%08x\n", im->ddr.sdram_cfg);
82 return CONFIG_SYS_DDR_SIZE;
88 * Initialize PCI Devices, report devices found
90 #ifndef CONFIG_PCI_PNP
91 static struct pci_config_table pci_mpc83xxmitx_config_table[] = {
99 pci_cfgfunc_config_device,
103 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}
109 volatile static struct pci_controller hose[] = {
111 #ifndef CONFIG_PCI_PNP
112 config_table:pci_mpc83xxmitx_config_table,
116 #ifndef CONFIG_PCI_PNP
117 config_table:pci_mpc83xxmitx_config_table,
121 #endif /* CONFIG_PCI */
125 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
127 #ifdef CONFIG_DDR_ECC
128 volatile ddr83xx_t *ddr = &im->ddr;
131 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
134 /* DDR SDRAM - Main SODIMM */
135 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
136 #ifdef CONFIG_SPD_EEPROM
139 msize = fixed_sdram();
142 #ifdef CONFIG_DDR_ECC
143 if (ddr->sdram_cfg & SDRAM_CFG_ECC_EN)
144 /* Unlike every other board, on the 83xx spd_sdram() returns
145 megabytes instead of just bytes. That's why we need to
146 multiple by 1MB when calling ddr_enable_ecc(). */
147 ddr_enable_ecc(msize * 1048576);
150 /* return total bus RAM size(bytes) */
151 gd->ram_size = msize * 1024 * 1024;
158 #ifdef CONFIG_TARGET_MPC8349ITX
159 puts("Board: Freescale MPC8349E-mITX\n");
161 puts("Board: Freescale MPC8349E-mITX-GP\n");
168 * Implement a work-around for a hardware problem with compact
171 * Program the UPM if compact flash is enabled.
173 int misc_init_f(void)
175 #ifdef CONFIG_VSC7385_ENET
176 volatile u32 *vsc7385_cpuctrl;
178 /* 0x1c0c0 is the VSC7385 CPU Control (CPUCTRL) Register. The power up
179 default of VSC7385 L1_IRQ and L2_IRQ requests are active high. That
180 means it is 0 when the IRQ is not active. This makes the wire-AND
181 logic always assert IRQ7 to CPU even if there is no request from the
182 switch. Since the compact flash and the switch share the same IRQ,
183 the Linux kernel will think that the compact flash is requesting irq
184 and get stuck when it tries to clear the IRQ. Thus we need to set
185 the L2_IRQ0 and L2_IRQ1 to active low.
187 The following code sets the L1_IRQ and L2_IRQ polarity to active low.
188 Without this code, compact flash will not work in Linux because
189 unlike U-Boot, Linux uses the IRQ, so this code is necessary if we
190 don't enable compact flash for U-Boot.
193 vsc7385_cpuctrl = (volatile u32 *)(CONFIG_SYS_VSC7385_BASE + 0x1c0c0);
194 *vsc7385_cpuctrl |= 0x0c;
197 #ifdef CONFIG_COMPACT_FLASH
198 /* UPM Table Configuration Code */
199 static uint UPMATable[] = {
200 0xcffffc00, 0x0fffff00, 0x0fafff00, 0x0fafff00,
201 0x0faffd00, 0x0faffc04, 0x0ffffc00, 0x3ffffc01,
202 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
203 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
204 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfff7fc00,
205 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
206 0xcffffc00, 0x0fffff00, 0x0ff3ff00, 0x0ff3ff00,
207 0x0ff3fe00, 0x0ffffc00, 0x3ffffc05, 0xfffffc00,
208 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
209 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
210 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
211 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
212 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
213 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00,
214 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01,
215 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01
217 volatile immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
219 set_lbc_br(3, CONFIG_SYS_BR3_PRELIM);
220 set_lbc_or(3, CONFIG_SYS_OR3_PRELIM);
222 /* Program the MAMR. RFEN=0, OP=00, UWPL=1, AM=000, DS=01, G0CL=000,
223 GPL4=0, RLF=0001, WLF=0001, TLF=0001, MAD=000000
225 immap->im_lbc.mamr = 0x08404440;
227 upmconfig(0, UPMATable, sizeof(UPMATable) / sizeof(UPMATable[0]));
229 puts("UPMA: Configured for compact flash\n");
236 * Miscellaneous late-boot configurations
238 * Make sure the EEPROM has the HRCW correctly programmed.
239 * Make sure the RTC is correctly programmed.
241 * The MPC8349E-mITX can be configured to load the HRCW from
242 * EEPROM instead of flash. This is controlled via jumpers
243 * LGPL0, 1, and 3. Normally, these jumpers are set to 000 (all
244 * jumpered), but if they're set to 001 or 010, then the HRCW is
245 * read from the "I2C EEPROM".
247 * This function makes sure that the I2C EEPROM is programmed
250 * If a VSC7385 microcode image is present, then upload it.
252 int misc_init_r(void)
256 #if defined(CONFIG_SYS_I2C)
257 unsigned int orig_bus = i2c_get_bus_num();
260 #ifdef CONFIG_SYS_I2C_RTC_ADDR
264 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
265 static u8 eeprom_data[] = /* HRCW data */
267 0xAA, 0x55, 0xAA, /* Preamble */
268 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
269 0x02, 0x40, /* RCWL ADDR=0x0_0900 */
270 (CONFIG_SYS_HRCW_LOW >> 24) & 0xFF,
271 (CONFIG_SYS_HRCW_LOW >> 16) & 0xFF,
272 (CONFIG_SYS_HRCW_LOW >> 8) & 0xFF,
273 CONFIG_SYS_HRCW_LOW & 0xFF,
274 0x7C, /* ACS=0, BYTE_EN=1111, CONT=1 */
275 0x02, 0x41, /* RCWH ADDR=0x0_0904 */
276 (CONFIG_SYS_HRCW_HIGH >> 24) & 0xFF,
277 (CONFIG_SYS_HRCW_HIGH >> 16) & 0xFF,
278 (CONFIG_SYS_HRCW_HIGH >> 8) & 0xFF,
279 CONFIG_SYS_HRCW_HIGH & 0xFF
282 u8 data[sizeof(eeprom_data)];
285 printf("Board revision: ");
287 if (i2c_read(CONFIG_SYS_I2C_8574A_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
288 printf("%u.%u (PCF8475A)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
289 else if (i2c_read(CONFIG_SYS_I2C_8574_ADDR2, 0, 0, &i2c_data, sizeof(i2c_data)) == 0)
290 printf("%u.%u (PCF8475)\n", (i2c_data & 0x02) >> 1, i2c_data & 0x01);
296 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR
299 if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, data, sizeof(data)) == 0) {
300 if (memcmp(data, eeprom_data, sizeof(data)) != 0) {
302 (CONFIG_SYS_I2C_EEPROM_ADDR, 0, 2, eeprom_data,
303 sizeof(eeprom_data)) != 0) {
304 puts("Failure writing the HRCW to EEPROM via I2C.\n");
309 puts("Failure reading the HRCW from EEPROM via I2C.\n");
314 #ifdef CONFIG_SYS_I2C_RTC_ADDR
317 if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data, sizeof(ds1339_data))
320 /* Work-around for MPC8349E-mITX bug #13601.
321 If the RTC does not contain valid register values, the DS1339
322 Linux driver will not work.
325 /* Make sure status register bits 6-2 are zero */
326 ds1339_data[0x0f] &= ~0x7c;
328 /* Check for a valid day register value */
329 ds1339_data[0x03] &= ~0xf8;
330 if (ds1339_data[0x03] == 0) {
331 ds1339_data[0x03] = 1;
334 /* Check for a valid date register value */
335 ds1339_data[0x04] &= ~0xc0;
336 if ((ds1339_data[0x04] == 0) ||
337 ((ds1339_data[0x04] & 0x0f) > 9) ||
338 (ds1339_data[0x04] >= 0x32)) {
339 ds1339_data[0x04] = 1;
342 /* Check for a valid month register value */
343 ds1339_data[0x05] &= ~0x60;
345 if ((ds1339_data[0x05] == 0) ||
346 ((ds1339_data[0x05] & 0x0f) > 9) ||
347 ((ds1339_data[0x05] >= 0x13)
348 && (ds1339_data[0x05] <= 0x19))) {
349 ds1339_data[0x05] = 1;
352 /* Enable Oscillator and rate select */
353 ds1339_data[0x0e] = 0x1c;
355 /* Work-around for MPC8349E-mITX bug #13330.
356 Ensure that the RTC control register contains the value 0x1c.
357 This affects SATA performance.
361 (CONFIG_SYS_I2C_RTC_ADDR, 0, 1, ds1339_data,
362 sizeof(ds1339_data))) {
363 puts("Failure writing to the RTC via I2C.\n");
367 puts("Failure reading from the RTC via I2C.\n");
372 i2c_set_bus_num(orig_bus);
375 #ifdef CONFIG_VSC7385_IMAGE
376 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
377 CONFIG_VSC7385_IMAGE_SIZE)) {
378 puts("Failure uploading VSC7385 microcode.\n");
386 #if defined(CONFIG_OF_BOARD_SETUP)
387 int ft_board_setup(void *blob, bd_t *bd)
389 ft_cpu_setup(blob, bd);
391 ft_pci_setup(blob, bd);