1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2006-2009 Freescale Semiconductor, Inc.
7 * PCI Configuration space access support for MPC83xx PCI Bridge
16 #include <asm/fsl_i2c.h>
17 #include "../common/pq-mds-pib.h"
19 static struct pci_region pci1_regions[] = {
21 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
22 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
23 size: CONFIG_SYS_PCI1_MEM_SIZE,
24 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
27 bus_start: CONFIG_SYS_PCI1_IO_BASE,
28 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
29 size: CONFIG_SYS_PCI1_IO_SIZE,
33 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
34 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
35 size: CONFIG_SYS_PCI1_MMIO_SIZE,
40 #ifdef CONFIG_MPC83XX_PCI2
41 static struct pci_region pci2_regions[] = {
43 bus_start: CONFIG_SYS_PCI2_MEM_BASE,
44 phys_start: CONFIG_SYS_PCI2_MEM_PHYS,
45 size: CONFIG_SYS_PCI2_MEM_SIZE,
46 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
49 bus_start: CONFIG_SYS_PCI2_IO_BASE,
50 phys_start: CONFIG_SYS_PCI2_IO_PHYS,
51 size: CONFIG_SYS_PCI2_IO_SIZE,
55 bus_start: CONFIG_SYS_PCI2_MMIO_BASE,
56 phys_start: CONFIG_SYS_PCI2_MMIO_PHYS,
57 size: CONFIG_SYS_PCI2_MMIO_SIZE,
63 void pci_init_board(void)
64 #ifdef CONFIG_PCISLAVE
66 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
67 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
68 volatile pcictrl83xx_t *pci_ctrl = &immr->pci_ctrl[0];
69 struct pci_region *reg[] = { pci1_regions };
71 /* Configure PCI Local Access Windows */
72 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
73 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_1G;
75 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
76 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_4M;
78 mpc83xx_pci_init(1, reg);
81 * Configure PCI Inbound Translation Windows
83 pci_ctrl[0].pitar0 = 0x0;
84 pci_ctrl[0].pibar0 = 0x0;
85 pci_ctrl[0].piwar0 = PIWAR_EN | PIWAR_RTT_SNOOP |
86 PIWAR_WTT_SNOOP | PIWAR_IWS_4K;
88 pci_ctrl[0].pitar1 = 0x0;
89 pci_ctrl[0].pibar1 = 0x0;
90 pci_ctrl[0].piebar1 = 0x0;
91 pci_ctrl[0].piwar1 &= ~PIWAR_EN;
93 pci_ctrl[0].pitar2 = 0x0;
94 pci_ctrl[0].pibar2 = 0x0;
95 pci_ctrl[0].piebar2 = 0x0;
96 pci_ctrl[0].piwar2 &= ~PIWAR_EN;
98 /* Unlock the configuration bit */
99 mpc83xx_pcislave_unlock(0);
100 printf("PCI: Agent mode enabled\n");
104 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
105 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
106 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
107 #ifndef CONFIG_MPC83XX_PCI2
108 struct pci_region *reg[] = { pci1_regions };
110 struct pci_region *reg[] = { pci1_regions, pci2_regions };
113 /* initialize the PCA9555PW IO expander on the PIB board */
116 #if defined(CONFIG_PCI_66M)
117 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
118 printf("PCI clock is 66MHz\n");
119 #elif defined(CONFIG_PCI_33M)
120 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2 |
121 OCCR_PCICD0 | OCCR_PCICD1 | OCCR_PCICD2 | OCCR_PCICR;
122 printf("PCI clock is 33MHz\n");
124 clk->occr = OCCR_PCICOE0 | OCCR_PCICOE1 | OCCR_PCICOE2;
125 printf("PCI clock is 66MHz\n");
129 /* Configure PCI Local Access Windows */
130 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
131 pci_law[0].ar = LAWAR_EN | LAWAR_SIZE_512M;
133 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
134 pci_law[1].ar = LAWAR_EN | LAWAR_SIZE_1M;
138 #ifndef CONFIG_MPC83XX_PCI2
139 mpc83xx_pci_init(1, reg);
141 mpc83xx_pci_init(2, reg);
144 #endif /* CONFIG_PCISLAVE */