2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Michael Barkowski <michael.barkowski@freescale.com>
5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
19 #include <linux/libfdt.h>
20 #if defined(CONFIG_PCI)
25 DECLARE_GLOBAL_DATA_PTR;
27 const qe_iop_conf_t qe_iop_conf_tab[] = {
29 {1, 0, 1, 0, 1}, /* TxD0 */
30 {1, 1, 1, 0, 1}, /* TxD1 */
31 {1, 2, 1, 0, 1}, /* TxD2 */
32 {1, 3, 1, 0, 1}, /* TxD3 */
33 {1, 9, 1, 0, 1}, /* TxER */
34 {1, 12, 1, 0, 1}, /* TxEN */
35 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
37 {1, 4, 2, 0, 1}, /* RxD0 */
38 {1, 5, 2, 0, 1}, /* RxD1 */
39 {1, 6, 2, 0, 1}, /* RxD2 */
40 {1, 7, 2, 0, 1}, /* RxD3 */
41 {1, 8, 2, 0, 1}, /* RxER */
42 {1, 10, 2, 0, 1}, /* RxDV */
43 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
44 {1, 11, 2, 0, 1}, /* COL */
45 {1, 13, 2, 0, 1}, /* CRS */
48 {0, 18, 1, 0, 1}, /* TxD0 */
49 {0, 19, 1, 0, 1}, /* TxD1 */
50 {0, 20, 1, 0, 1}, /* TxD2 */
51 {0, 21, 1, 0, 1}, /* TxD3 */
52 {0, 27, 1, 0, 1}, /* TxER */
53 {0, 30, 1, 0, 1}, /* TxEN */
54 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
56 {0, 22, 2, 0, 1}, /* RxD0 */
57 {0, 23, 2, 0, 1}, /* RxD1 */
58 {0, 24, 2, 0, 1}, /* RxD2 */
59 {0, 25, 2, 0, 1}, /* RxD3 */
60 {0, 26, 1, 0, 1}, /* RxER */
61 {0, 28, 2, 0, 1}, /* Rx_DV */
62 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
63 {0, 29, 2, 0, 1}, /* COL */
64 {0, 31, 2, 0, 1}, /* CRS */
66 {3, 4, 3, 0, 2}, /* MDIO */
67 {3, 5, 1, 0, 2}, /* MDC */
69 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
72 int fixed_sdram(void);
76 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
79 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
82 /* DDR SDRAM - Main SODIMM */
83 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
85 msize = fixed_sdram();
87 /* set total bus SDRAM size(bytes) -- DDR */
88 gd->ram_size = msize * 1024 * 1024;
93 /*************************************************************************
94 * fixed sdram init -- doesn't use serial presence detect.
95 ************************************************************************/
98 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
103 msize = CONFIG_SYS_DDR_SIZE;
104 for (ddr_size = msize << 20, ddr_size_log2 = 0;
105 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
110 im->sysconf.ddrlaw[0].ar =
111 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
112 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
113 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
114 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
115 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
116 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
117 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
118 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
119 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
120 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
121 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
122 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
123 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
124 __asm__ __volatile__ ("sync");
127 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
128 __asm__ __volatile__ ("sync");
134 puts("Board: Freescale MPC8323ERDB\n");
138 static struct pci_region pci_regions[] = {
140 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
141 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
142 size: CONFIG_SYS_PCI1_MEM_SIZE,
143 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
146 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
147 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
148 size: CONFIG_SYS_PCI1_MMIO_SIZE,
149 flags: PCI_REGION_MEM
152 bus_start: CONFIG_SYS_PCI1_IO_BASE,
153 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
154 size: CONFIG_SYS_PCI1_IO_SIZE,
159 void pci_init_board(void)
161 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
162 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
163 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
164 struct pci_region *reg[] = { pci_regions };
166 /* Enable all 3 PCI_CLK_OUTPUTs. */
167 clk->occr |= 0xe0000000;
169 /* Configure PCI Local Access Windows */
170 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
171 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
173 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
174 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
176 mpc83xx_pci_init(1, reg);
179 #if defined(CONFIG_OF_BOARD_SETUP)
180 int ft_board_setup(void *blob, bd_t *bd)
182 ft_cpu_setup(blob, bd);
184 ft_pci_setup(blob, bd);
191 #if defined(CONFIG_SYS_I2C_MAC_OFFSET)
192 int mac_read_from_eeprom(void)
197 unsigned int crc = 0;
198 unsigned char enetvar[32];
200 /* Read MAC addresses from EEPROM */
201 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
202 printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
203 CONFIG_SYS_I2C_EEPROM_ADDR);
207 memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
209 if (crc32(crc, buf, 24) == crc_buf) {
210 printf("Reading MAC from EEPROM\n");
211 for (i = 0; i < 4; i++) {
212 if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
214 "%02X:%02X:%02X:%02X:%02X:%02X",
215 buf[i * 6], buf[i * 6 + 1],
216 buf[i * 6 + 2], buf[i * 6 + 3],
217 buf[i * 6 + 4], buf[i * 6 + 5]);
218 sprintf((char *)enetvar,
219 i ? "eth%daddr" : "ethaddr", i);
220 env_set((char *)enetvar, str);
227 #endif /* CONFIG_I2C_MAC_OFFSET */