2 * Copyright (C) 2007 Freescale Semiconductor, Inc.
4 * Michael Barkowski <michael.barkowski@freescale.com>
5 * Based on mpc832xmds file by Dave Liu <daveliu@freescale.com>
7 * This program is free software; you can redistribute it and/or modify it
8 * under the terms of the GNU General Public License version 2 as published
9 * by the Free Software Foundation.
15 #include <fdt_support.h>
22 #include <linux/libfdt.h>
23 #include <u-boot/crc.h>
24 #if defined(CONFIG_PCI)
29 DECLARE_GLOBAL_DATA_PTR;
31 const qe_iop_conf_t qe_iop_conf_tab[] = {
33 {1, 0, 1, 0, 1}, /* TxD0 */
34 {1, 1, 1, 0, 1}, /* TxD1 */
35 {1, 2, 1, 0, 1}, /* TxD2 */
36 {1, 3, 1, 0, 1}, /* TxD3 */
37 {1, 9, 1, 0, 1}, /* TxER */
38 {1, 12, 1, 0, 1}, /* TxEN */
39 {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */
41 {1, 4, 2, 0, 1}, /* RxD0 */
42 {1, 5, 2, 0, 1}, /* RxD1 */
43 {1, 6, 2, 0, 1}, /* RxD2 */
44 {1, 7, 2, 0, 1}, /* RxD3 */
45 {1, 8, 2, 0, 1}, /* RxER */
46 {1, 10, 2, 0, 1}, /* RxDV */
47 {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */
48 {1, 11, 2, 0, 1}, /* COL */
49 {1, 13, 2, 0, 1}, /* CRS */
52 {0, 18, 1, 0, 1}, /* TxD0 */
53 {0, 19, 1, 0, 1}, /* TxD1 */
54 {0, 20, 1, 0, 1}, /* TxD2 */
55 {0, 21, 1, 0, 1}, /* TxD3 */
56 {0, 27, 1, 0, 1}, /* TxER */
57 {0, 30, 1, 0, 1}, /* TxEN */
58 {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */
60 {0, 22, 2, 0, 1}, /* RxD0 */
61 {0, 23, 2, 0, 1}, /* RxD1 */
62 {0, 24, 2, 0, 1}, /* RxD2 */
63 {0, 25, 2, 0, 1}, /* RxD3 */
64 {0, 26, 1, 0, 1}, /* RxER */
65 {0, 28, 2, 0, 1}, /* Rx_DV */
66 {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */
67 {0, 29, 2, 0, 1}, /* COL */
68 {0, 31, 2, 0, 1}, /* CRS */
70 {3, 4, 3, 0, 2}, /* MDIO */
71 {3, 5, 1, 0, 2}, /* MDC */
73 {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */
76 int fixed_sdram(void);
80 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
83 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32) im)
86 /* DDR SDRAM - Main SODIMM */
87 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR;
89 msize = fixed_sdram();
91 /* set total bus SDRAM size(bytes) -- DDR */
92 gd->ram_size = msize * 1024 * 1024;
97 /*************************************************************************
98 * fixed sdram init -- doesn't use serial presence detect.
99 ************************************************************************/
100 int fixed_sdram(void)
102 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
107 msize = CONFIG_SYS_DDR_SIZE;
108 for (ddr_size = msize << 20, ddr_size_log2 = 0;
109 (ddr_size > 1); ddr_size = ddr_size >> 1, ddr_size_log2++) {
114 im->sysconf.ddrlaw[0].ar =
115 LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE);
116 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_CLK_CNTL;
117 im->ddr.csbnds[0].csbnds = CONFIG_SYS_DDR_CS0_BNDS;
118 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
119 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
120 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
121 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
122 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
123 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
124 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
125 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
126 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
127 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
128 __asm__ __volatile__ ("sync");
131 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
132 __asm__ __volatile__ ("sync");
138 puts("Board: Freescale MPC8323ERDB\n");
142 static struct pci_region pci_regions[] = {
144 bus_start: CONFIG_SYS_PCI1_MEM_BASE,
145 phys_start: CONFIG_SYS_PCI1_MEM_PHYS,
146 size: CONFIG_SYS_PCI1_MEM_SIZE,
147 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
150 bus_start: CONFIG_SYS_PCI1_MMIO_BASE,
151 phys_start: CONFIG_SYS_PCI1_MMIO_PHYS,
152 size: CONFIG_SYS_PCI1_MMIO_SIZE,
153 flags: PCI_REGION_MEM
156 bus_start: CONFIG_SYS_PCI1_IO_BASE,
157 phys_start: CONFIG_SYS_PCI1_IO_PHYS,
158 size: CONFIG_SYS_PCI1_IO_SIZE,
163 void pci_init_board(void)
165 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
166 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
167 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
168 struct pci_region *reg[] = { pci_regions };
170 /* Enable all 3 PCI_CLK_OUTPUTs. */
171 clk->occr |= 0xe0000000;
173 /* Configure PCI Local Access Windows */
174 pci_law[0].bar = CONFIG_SYS_PCI1_MEM_PHYS & LAWBAR_BAR;
175 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
177 pci_law[1].bar = CONFIG_SYS_PCI1_IO_PHYS & LAWBAR_BAR;
178 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
180 mpc83xx_pci_init(1, reg);
183 #if defined(CONFIG_OF_BOARD_SETUP)
184 int ft_board_setup(void *blob, bd_t *bd)
186 ft_cpu_setup(blob, bd);
188 ft_pci_setup(blob, bd);
195 #if defined(CONFIG_SYS_I2C_MAC_OFFSET)
196 int mac_read_from_eeprom(void)
201 unsigned int crc = 0;
202 unsigned char enetvar[32];
204 /* Read MAC addresses from EEPROM */
205 if (eeprom_read(CONFIG_SYS_I2C_EEPROM_ADDR, CONFIG_SYS_I2C_MAC_OFFSET, buf, 28)) {
206 printf("\nEEPROM @ 0x%02x read FAILED!!!\n",
207 CONFIG_SYS_I2C_EEPROM_ADDR);
211 memcpy(&crc_buf, &buf[24], sizeof(uint32_t));
213 if (crc32(crc, buf, 24) == crc_buf) {
214 printf("Reading MAC from EEPROM\n");
215 for (i = 0; i < 4; i++) {
216 if (memcmp(&buf[i * 6], "\0\0\0\0\0\0", 6)) {
218 "%02X:%02X:%02X:%02X:%02X:%02X",
219 buf[i * 6], buf[i * 6 + 1],
220 buf[i * 6 + 2], buf[i * 6 + 3],
221 buf[i * 6 + 4], buf[i * 6 + 5]);
222 sprintf((char *)enetvar,
223 i ? "eth%daddr" : "ethaddr", i);
224 env_set((char *)enetvar, str);
231 #endif /* CONFIG_I2C_MAC_OFFSET */