1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
5 * Authors: Nick.Spence@freescale.com
6 * Wilson.Lo@freescale.com
7 * scottwood@freescale.com
13 #include <spd_sdram.h>
14 #include <linux/delay.h>
16 #include <asm/bitops.h>
19 #include <asm/processor.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 static void resume_from_sleep(void)
25 u32 magic = *(u32 *)0;
27 typedef void (*func_t)(void);
28 func_t resume = *(func_t *)4;
30 if (magic == 0xf5153ae5)
33 gd->flags &= ~GD_FLG_SILENT;
34 puts("\nResume from sleep failed: bad magic word\n");
37 /* Fixed sdram init -- doesn't use serial presence detect.
39 * This is useful for faster booting in configs where the RAM is unlikely
40 * to be changed, or for things like NAND booting where space is tight.
42 #ifndef CONFIG_SYS_RAMBOOT
43 static long fixed_sdram(void)
45 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
46 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
47 u32 msize_log2 = __ilog2(msize);
49 im->sysconf.ddrlaw[0].bar = CONFIG_SYS_SDRAM_BASE & 0xfffff000;
50 im->sysconf.ddrlaw[0].ar = LBLAWAR_EN | (msize_log2 - 1);
51 im->sysconf.ddrcdr = CONFIG_SYS_DDRCDR_VALUE;
54 * Erratum DDR3 requires a 50ms delay after clearing DDRCDR[DDR_cfg],
55 * or the DDR2 controller may fail to initialize correctly.
59 im->ddr.csbnds[0].csbnds = (msize - 1) >> 24;
60 im->ddr.cs_config[0] = CONFIG_SYS_DDR_CS0_CONFIG;
62 /* Currently we use only one CS, so disable the other bank. */
63 im->ddr.cs_config[1] = 0;
65 im->ddr.sdram_clk_cntl = CONFIG_SYS_DDR_SDRAM_CLK_CNTL;
66 im->ddr.timing_cfg_3 = CONFIG_SYS_DDR_TIMING_3;
67 im->ddr.timing_cfg_1 = CONFIG_SYS_DDR_TIMING_1;
68 im->ddr.timing_cfg_2 = CONFIG_SYS_DDR_TIMING_2;
69 im->ddr.timing_cfg_0 = CONFIG_SYS_DDR_TIMING_0;
71 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
72 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG | SDRAM_CFG_BI;
74 im->ddr.sdram_cfg = CONFIG_SYS_DDR_SDRAM_CFG;
76 im->ddr.sdram_cfg2 = CONFIG_SYS_DDR_SDRAM_CFG2;
77 im->ddr.sdram_mode = CONFIG_SYS_DDR_MODE;
78 im->ddr.sdram_mode2 = CONFIG_SYS_DDR_MODE2;
80 im->ddr.sdram_interval = CONFIG_SYS_DDR_INTERVAL;
83 /* enable DDR controller */
84 im->ddr.sdram_cfg |= SDRAM_CFG_MEM_EN;
90 static long fixed_sdram(void)
92 return CONFIG_SYS_DDR_SIZE * 1024 * 1024;
94 #endif /* CONFIG_SYS_RAMBOOT */
98 volatile immap_t *im = (volatile immap_t *)CONFIG_SYS_IMMR;
101 if ((im->sysconf.immrbar & IMMRBAR_BASE_ADDR) != (u32)im)
105 msize = fixed_sdram();
107 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
110 /* set total bus SDRAM size(bytes) -- DDR */
111 gd->ram_size = msize;