1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2007 Freescale Semiconductor, Inc.
5 * Author: Scott Wood <scottwood@freescale.com>
6 * Dave Liu <daveliu@freescale.com>
14 #include <linux/libfdt.h>
15 #include <fdt_support.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 int board_early_init_f(void)
27 volatile immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
29 if (im->pmc.pmccr1 & PMCCR1_POWER_OFF)
30 gd->flags |= GD_FLG_SILENT;
35 #ifndef CONFIG_NAND_SPL
37 static u8 read_board_info(void)
42 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
50 static const char * const rev_str[] = {
60 info = read_board_info();
61 i = (!info) ? 4: info & 0x03;
63 printf("Board: Freescale MPC8315ERDB Rev %s\n", rev_str[i]);
68 static struct pci_region pci_regions[] = {
70 bus_start: CONFIG_SYS_PCI_MEM_BASE,
71 phys_start: CONFIG_SYS_PCI_MEM_PHYS,
72 size: CONFIG_SYS_PCI_MEM_SIZE,
73 flags: PCI_REGION_MEM | PCI_REGION_PREFETCH
76 bus_start: CONFIG_SYS_PCI_MMIO_BASE,
77 phys_start: CONFIG_SYS_PCI_MMIO_PHYS,
78 size: CONFIG_SYS_PCI_MMIO_SIZE,
82 bus_start: CONFIG_SYS_PCI_IO_BASE,
83 phys_start: CONFIG_SYS_PCI_IO_PHYS,
84 size: CONFIG_SYS_PCI_IO_SIZE,
89 static struct pci_region pcie_regions_0[] = {
91 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
92 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
93 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
94 .flags = PCI_REGION_MEM,
97 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
98 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
99 .size = CONFIG_SYS_PCIE1_IO_SIZE,
100 .flags = PCI_REGION_IO,
104 static struct pci_region pcie_regions_1[] = {
106 .bus_start = CONFIG_SYS_PCIE2_MEM_BASE,
107 .phys_start = CONFIG_SYS_PCIE2_MEM_PHYS,
108 .size = CONFIG_SYS_PCIE2_MEM_SIZE,
109 .flags = PCI_REGION_MEM,
112 .bus_start = CONFIG_SYS_PCIE2_IO_BASE,
113 .phys_start = CONFIG_SYS_PCIE2_IO_PHYS,
114 .size = CONFIG_SYS_PCIE2_IO_SIZE,
115 .flags = PCI_REGION_IO,
119 void pci_init_board(void)
121 volatile immap_t *immr = (volatile immap_t *)CONFIG_SYS_IMMR;
122 volatile sysconf83xx_t *sysconf = &immr->sysconf;
123 volatile clk83xx_t *clk = (volatile clk83xx_t *)&immr->clk;
124 volatile law83xx_t *pci_law = immr->sysconf.pcilaw;
125 volatile law83xx_t *pcie_law = sysconf->pcielaw;
126 struct pci_region *reg[] = { pci_regions };
127 struct pci_region *pcie_reg[] = { pcie_regions_0, pcie_regions_1, };
129 /* Enable all 3 PCI_CLK_OUTPUTs. */
130 clk->occr |= 0xe0000000;
133 * Configure PCI Local Access Windows
135 pci_law[0].bar = CONFIG_SYS_PCI_MEM_PHYS & LAWBAR_BAR;
136 pci_law[0].ar = LBLAWAR_EN | LBLAWAR_512MB;
138 pci_law[1].bar = CONFIG_SYS_PCI_IO_PHYS & LAWBAR_BAR;
139 pci_law[1].ar = LBLAWAR_EN | LBLAWAR_1MB;
141 mpc83xx_pci_init(1, reg);
143 /* Configure the clock for PCIE controller */
144 clrsetbits_be32(&clk->sccr, SCCR_PCIEXP1CM | SCCR_PCIEXP2CM,
145 SCCR_PCIEXP1CM_1 | SCCR_PCIEXP2CM_1);
147 /* Deassert the resets in the control register */
148 out_be32(&sysconf->pecr1, 0xE0008000);
149 out_be32(&sysconf->pecr2, 0xE0008000);
152 /* Configure PCI Express Local Access Windows */
153 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
154 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
156 out_be32(&pcie_law[1].bar, CONFIG_SYS_PCIE2_BASE & LAWBAR_BAR);
157 out_be32(&pcie_law[1].ar, LBLAWAR_EN | LBLAWAR_512MB);
159 mpc83xx_pcie_init(2, pcie_reg);
162 #if defined(CONFIG_OF_BOARD_SETUP)
163 void fdt_tsec1_fixup(void *fdt, bd_t *bd)
165 const char disabled[] = "disabled";
169 if (hwconfig_arg_cmp("board_type", "tsec1")) {
171 } else if (!hwconfig_arg_cmp("board_type", "ulpi")) {
172 printf("NOTICE: No or unknown board_type hwconfig specified.\n"
173 " Assuming board with TSEC1.\n");
177 ret = fdt_path_offset(fdt, "/aliases");
179 printf("WARNING: can't find /aliases node\n");
183 path = fdt_getprop(fdt, ret, "ethernet0", NULL);
185 printf("WARNING: can't find ethernet0 alias\n");
189 do_fixup_by_path(fdt, path, "status", disabled, sizeof(disabled), 1);
192 int ft_board_setup(void *blob, bd_t *bd)
194 ft_cpu_setup(blob, bd);
196 ft_pci_setup(blob, bd);
198 fsl_fdt_fixup_dr_usb(blob, bd);
199 fdt_tsec1_fixup(blob, bd);
205 int board_eth_init(bd_t *bis)
207 cpu_eth_init(bis); /* Initialize TSECs first */
208 return pci_eth_init(bis);
211 #else /* CONFIG_NAND_SPL */
215 puts("Board: Freescale MPC8315ERDB\n");
219 void board_init_f(ulong bootflag)
221 board_early_init_f();
222 NS16550_init((NS16550_t)(CONFIG_SYS_IMMR + 0x4500),
223 CONFIG_SYS_NS16550_CLK / 16 / CONFIG_BAUDRATE);
224 puts("NAND boot... ");
227 relocate_code(CONFIG_SYS_NAND_U_BOOT_RELOC + 0x10000, (gd_t *)gd,
228 CONFIG_SYS_NAND_U_BOOT_RELOC);
231 void board_init_r(gd_t *gd, ulong dest_addr)
238 if (gd->flags & GD_FLG_SILENT)
242 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), '\r');
244 NS16550_putc((NS16550_t)(CONFIG_SYS_IMMR + 0x4500), c);
247 #endif /* CONFIG_NAND_SPL */