1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright (C) 2010 Freescale Semiconductor, Inc.
4 * Copyright (C) 2010 Ilya Yanok, Emcraft Systems, yanok@emcraft.com
12 #include <linux/libfdt.h>
13 #include <fdt_support.h>
18 #include <fsl_esdhc.h>
20 #include <asm/fsl_serdes.h>
21 #include <asm/fsl_mpc83xx_serdes.h>
24 * The following are used to control the SPI chip selects for the SPI command.
26 #ifdef CONFIG_MPC8XXX_SPI
28 #define SPI_CS_MASK 0x00400000
30 int spi_cs_is_valid(unsigned int bus, unsigned int cs)
32 return bus == 0 && cs == 0;
35 void spi_cs_activate(struct spi_slave *slave)
37 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
40 clrbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
43 void spi_cs_deactivate(struct spi_slave *slave)
45 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
48 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
50 #endif /* CONFIG_MPC8XXX_SPI */
52 #ifdef CONFIG_FSL_ESDHC
53 int board_mmc_init(bd_t *bd)
55 return fsl_esdhc_mmc_init(bd);
59 static u8 read_board_info(void)
64 if (i2c_read(CONFIG_SYS_I2C_PCF8574A_ADDR, 0, 0, &val8, 1) == 0)
72 static const char * const rev_str[] = {
82 info = read_board_info();
83 i = (!info) ? 4 : info & 0x03;
85 printf("Board: Freescale MPC8308RDB Rev %s\n", rev_str[i]);
90 static struct pci_region pcie_regions_0[] = {
92 .bus_start = CONFIG_SYS_PCIE1_MEM_BASE,
93 .phys_start = CONFIG_SYS_PCIE1_MEM_PHYS,
94 .size = CONFIG_SYS_PCIE1_MEM_SIZE,
95 .flags = PCI_REGION_MEM,
98 .bus_start = CONFIG_SYS_PCIE1_IO_BASE,
99 .phys_start = CONFIG_SYS_PCIE1_IO_PHYS,
100 .size = CONFIG_SYS_PCIE1_IO_SIZE,
101 .flags = PCI_REGION_IO,
105 void pci_init_board(void)
107 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
108 sysconf83xx_t *sysconf = &immr->sysconf;
109 law83xx_t *pcie_law = sysconf->pcielaw;
110 struct pci_region *pcie_reg[] = { pcie_regions_0 };
112 fsl_setup_serdes(CONFIG_FSL_SERDES1, FSL_SERDES_PROTO_PEX,
113 FSL_SERDES_CLK_100, FSL_SERDES_VDD_1V);
115 /* Deassert the resets in the control register */
116 out_be32(&sysconf->pecr1, 0xE0008000);
119 /* Configure PCI Express Local Access Windows */
120 out_be32(&pcie_law[0].bar, CONFIG_SYS_PCIE1_BASE & LAWBAR_BAR);
121 out_be32(&pcie_law[0].ar, LBLAWAR_EN | LBLAWAR_512MB);
123 mpc83xx_pcie_init(1, pcie_reg);
126 * Miscellaneous late-boot configurations
128 * If a VSC7385 microcode image is present, then upload it.
130 int misc_init_r(void)
132 #ifdef CONFIG_MPC8XXX_SPI
133 immap_t *immr = (immap_t *)CONFIG_SYS_IMMR;
134 sysconf83xx_t *sysconf = &immr->sysconf;
137 * Set proper bits in SICRH to allow SPI on header J8
139 * NOTE: this breaks the TSEC2 interface, attached to the Vitesse
140 * switch. The pinmux configuration does not have a fine enough
141 * granularity to support both simultaneously.
143 clrsetbits_be32(&sysconf->sicrh, SICRH_GPIO_A_TSEC2, SICRH_GPIO_A_GPIO);
144 puts("WARNING: SPI enabled, TSEC2 support is broken\n");
146 /* Set header J8 SPI chip select output, disabled */
147 setbits_be32(&immr->gpio[0].dir, SPI_CS_MASK);
148 setbits_be32(&immr->gpio[0].dat, SPI_CS_MASK);
151 #ifdef CONFIG_VSC7385_IMAGE
152 if (vsc7385_upload_firmware((void *) CONFIG_VSC7385_IMAGE,
153 CONFIG_VSC7385_IMAGE_SIZE)) {
154 puts("Failure uploading VSC7385 microcode.\n");
161 #if defined(CONFIG_OF_BOARD_SETUP)
162 int ft_board_setup(void *blob, bd_t *bd)
164 ft_cpu_setup(blob, bd);
165 fsl_fdt_fixup_dr_usb(blob, bd);
166 fdt_fixup_esdhc(blob, bd);
172 int board_eth_init(bd_t *bis)
176 /* Initialize TSECs first */
177 rv = cpu_eth_init(bis);
181 printf("ERROR: failed to initialize TSECs.\n");
183 rv = pci_eth_init(bis);
187 printf("ERROR: failed to initialize PCI Ethernet.\n");