2 * (C) Copyright 2007-2009 DENX Software Engineering
4 * See file CREDITS for list of people who contributed to this
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 of
10 * the License, or (at your option) any later version.
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
17 * You should have received a copy of the GNU General Public License
18 * along with this program; if not, write to the Free Software
19 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
25 #include <asm/bitops.h>
28 #include <asm/processor.h>
29 #include <fdt_support.h>
30 #ifdef CONFIG_MISC_INIT_R
34 DECLARE_GLOBAL_DATA_PTR;
36 extern int mpc5121_diu_init(void);
37 extern void ide_set_reset(int idereset);
40 #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \
41 CLOCK_SCCR1_LPC_EN | \
42 CLOCK_SCCR1_PSC_EN(CONFIG_PSC_CONSOLE) | \
43 CLOCK_SCCR1_PSCFIFO_EN | \
44 CLOCK_SCCR1_DDR_EN | \
45 CLOCK_SCCR1_FEC_EN | \
46 CLOCK_SCCR1_PATA_EN | \
47 CLOCK_SCCR1_PCI_EN | \
50 #define SCCR2_CLOCKS_EN (CLOCK_SCCR2_MEM_EN | \
51 CLOCK_SCCR2_SPDIF_EN | \
52 CLOCK_SCCR2_DIU_EN | \
55 #define CSAW_START(start) ((start) & 0xFFFF0000)
56 #define CSAW_STOP(start, size) (((start) + (size) - 1) >> 16)
58 long int fixed_sdram(void);
60 int board_early_init_f (void)
62 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
66 * Initialize Local Window for the CPLD registers access (CS2 selects
69 out_be32(&im->sysconf.lpcs2aw,
70 CSAW_START(CONFIG_SYS_CPLD_BASE) |
71 CSAW_STOP(CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_SIZE)
73 out_be32(&im->lpc.cs_cfg[2], CONFIG_SYS_CS2_CFG);
76 * According to MPC5121e RM, configuring local access windows should
77 * be followed by a dummy read of the config register that was
78 * modified last and an isync
80 lpcaw = in_be32(&im->sysconf.lpcs6aw);
81 __asm__ __volatile__ ("isync");
84 * Disable Boot NOR FLASH write protect - CPLD Reg 8 NOR FLASH Control
86 * Without this the flash identification routine fails, as it needs to issue
87 * write commands in order to establish the device ID.
90 #ifdef CONFIG_ADS5121_REV2
91 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
93 if (in_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08)) & 0x04) {
94 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0xC1);
96 /* running from Backup flash */
97 out_8((u8 *)(CONFIG_SYS_CPLD_BASE + 0x08), 0x32);
101 * Configure Flash Speed
103 out_be32(&im->lpc.cs_cfg[0], CONFIG_SYS_CS0_CFG);
105 spridr = in_be32(&im->sysconf.spridr);
107 if (SVR_MJREV (spridr) >= 2)
108 out_be32 (&im->lpc.altr, CONFIG_SYS_CS_ALETIMING);
113 out_be32 (&im->clk.sccr[0], SCCR1_CLOCKS_EN);
114 out_be32 (&im->clk.sccr[1], SCCR2_CLOCKS_EN);
115 #if defined(CONFIG_IIM) || defined(CONFIG_CMD_FUSE)
116 setbits_be32 (&im->clk.sccr[1], CLOCK_SCCR2_IIM_EN);
122 phys_size_t initdram (int board_type)
126 msize = fixed_sdram ();
132 * fixed sdram init -- the board doesn't use memory modules that have serial presence
133 * detect or similar mechanism for discovery of the DRAM settings
135 long int fixed_sdram (void)
137 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
138 u32 msize = CONFIG_SYS_DDR_SIZE * 1024 * 1024;
139 u32 msize_log2 = __ilog2 (msize);
142 /* Initialize IO Control */
143 out_be32 (&im->io_ctrl.io_control_mem, IOCTRL_MUX_DDR);
145 /* Initialize DDR Local Window */
146 out_be32 (&im->sysconf.ddrlaw.bar, CONFIG_SYS_DDR_BASE & 0xFFFFF000);
147 out_be32 (&im->sysconf.ddrlaw.ar, msize_log2 - 1);
150 * According to MPC5121e RM, configuring local access windows should
151 * be followed by a dummy read of the config register that was
152 * modified last and an isync
154 in_be32(&im->sysconf.ddrlaw.ar);
155 __asm__ __volatile__ ("isync");
158 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_EN);
160 /* Initialize DDR Priority Manager */
161 out_be32(&im->mddrc.prioman_config1, CONFIG_SYS_MDDRCGRP_PM_CFG1);
162 out_be32(&im->mddrc.prioman_config2, CONFIG_SYS_MDDRCGRP_PM_CFG2);
163 out_be32(&im->mddrc.hiprio_config, CONFIG_SYS_MDDRCGRP_HIPRIO_CFG);
164 out_be32(&im->mddrc.lut_table0_main_upper, CONFIG_SYS_MDDRCGRP_LUT0_MU);
165 out_be32(&im->mddrc.lut_table0_main_lower, CONFIG_SYS_MDDRCGRP_LUT0_ML);
166 out_be32(&im->mddrc.lut_table1_main_upper, CONFIG_SYS_MDDRCGRP_LUT1_MU);
167 out_be32(&im->mddrc.lut_table1_main_lower, CONFIG_SYS_MDDRCGRP_LUT1_ML);
168 out_be32(&im->mddrc.lut_table2_main_upper, CONFIG_SYS_MDDRCGRP_LUT2_MU);
169 out_be32(&im->mddrc.lut_table2_main_lower, CONFIG_SYS_MDDRCGRP_LUT2_ML);
170 out_be32(&im->mddrc.lut_table3_main_upper, CONFIG_SYS_MDDRCGRP_LUT3_MU);
171 out_be32(&im->mddrc.lut_table3_main_lower, CONFIG_SYS_MDDRCGRP_LUT3_ML);
172 out_be32(&im->mddrc.lut_table4_main_upper, CONFIG_SYS_MDDRCGRP_LUT4_MU);
173 out_be32(&im->mddrc.lut_table4_main_lower, CONFIG_SYS_MDDRCGRP_LUT4_ML);
174 out_be32(&im->mddrc.lut_table0_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT0_AU);
175 out_be32(&im->mddrc.lut_table0_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT0_AL);
176 out_be32(&im->mddrc.lut_table1_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT1_AU);
177 out_be32(&im->mddrc.lut_table1_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT1_AL);
178 out_be32(&im->mddrc.lut_table2_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT2_AU);
179 out_be32(&im->mddrc.lut_table2_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT2_AL);
180 out_be32(&im->mddrc.lut_table3_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT3_AU);
181 out_be32(&im->mddrc.lut_table3_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT3_AL);
182 out_be32(&im->mddrc.lut_table4_alternate_upper, CONFIG_SYS_MDDRCGRP_LUT4_AU);
183 out_be32(&im->mddrc.lut_table4_alternate_lower, CONFIG_SYS_MDDRCGRP_LUT4_AL);
185 /* Initialize MDDRC */
186 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG);
187 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0);
188 out_be32(&im->mddrc.ddr_time_config1, CONFIG_SYS_MDDRC_TIME_CFG1);
189 out_be32(&im->mddrc.ddr_time_config2, CONFIG_SYS_MDDRC_TIME_CFG2);
192 for (i = 0; i < 10; i++)
193 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
195 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
196 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
197 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
198 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
199 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
200 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
201 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
202 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
203 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
204 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
205 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
206 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM2);
207 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EM3);
208 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_EN_DLL);
209 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
210 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
211 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_RFSH);
212 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_INIT_DEV_OP);
213 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_OCD_DEFAULT);
214 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_PCHG_ALL);
215 out_be32(&im->mddrc.ddr_command, CONFIG_SYS_MICRON_NOP);
218 out_be32(&im->mddrc.ddr_time_config0, CONFIG_SYS_MDDRC_TIME_CFG0_RUN);
219 out_be32(&im->mddrc.ddr_sys_config, CONFIG_SYS_MDDRC_SYS_CFG_RUN);
224 int misc_init_r(void)
228 /* Using this for DIU init before the driver in linux takes over
229 * Enable the TFP410 Encoder (I2C address 0x38)
234 i2c_write(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
235 /* Verify if enabled */
237 i2c_read(0x38, 0x08, 1, &tmp_val, sizeof(tmp_val));
238 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
241 i2c_write(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
242 /* Verify if enabled */
244 i2c_read(0x38, 0x0A, 1, &tmp_val, sizeof(tmp_val));
245 debug("DVI Encoder Read: 0x%02lx\n", tmp_val);
247 #ifdef CONFIG_FSL_DIU_FB
248 # if !(defined(CONFIG_VIDEO) || defined(CONFIG_CFB_CONSOLE))
255 static iopin_t ioregs_init[] = {
256 /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */
258 offsetof(struct ioctrl512x, io_control_spdif_txclk), 3, 0,
259 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
260 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
262 /* Set highest Slew on 9 PATA pins */
264 offsetof(struct ioctrl512x, io_control_pata_ce1), 9, 1,
265 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
266 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
268 /* FUNC1=FEC_COL Sets Next 15 to FEC pads */
270 offsetof(struct ioctrl512x, io_control_psc0_0), 15, 0,
271 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
272 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
274 /* FUNC1=SPDIF_TXCLK */
276 offsetof(struct ioctrl512x, io_control_lpc_cs1), 1, 0,
277 IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
278 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
280 /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */
282 offsetof(struct ioctrl512x, io_control_i2c1_scl), 2, 0,
283 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
284 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
288 offsetof(struct ioctrl512x, io_control_psc6_0), 1, 0,
289 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
290 IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3)
292 /* FUNC2=DIU_HSYNC */
294 offsetof(struct ioctrl512x, io_control_psc6_1), 1, 0,
295 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
296 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
298 /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */
300 offsetof(struct ioctrl512x, io_control_psc6_4), 26, 0,
301 IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) |
302 IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3)
306 static iopin_t rev2_silicon_pci_ioregs_init[] = {
307 /* FUNC0=PCI Sets next 54 to PCI pads */
309 offsetof(struct ioctrl512x, io_control_pci_ad31), 54, 0,
310 IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_DS(0)
314 int checkboard (void)
316 ushort brd_rev = *(vu_short *) (CONFIG_SYS_CPLD_BASE + 0x00);
317 uchar cpld_rev = *(vu_char *) (CONFIG_SYS_CPLD_BASE + 0x02);
318 volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
319 u32 spridr = in_be32(&im->sysconf.spridr);
321 printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n",
324 /* initialize function mux & slew rate IO inter alia on IO Pins */
325 iopin_initialize(ioregs_init, ARRAY_SIZE(ioregs_init));
327 if (SVR_MJREV (spridr) >= 2)
328 iopin_initialize(rev2_silicon_pci_ioregs_init, 1);
333 #if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP)
334 void ft_board_setup(void *blob, bd_t *bd)
336 ft_cpu_setup(blob, bd);
337 fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize);
339 #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */