2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007 Freescale Semiconductor, Inc.
6 * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
29 #include <asm/immap.h>
32 typedef unsigned char FLASH_PORT_WIDTH;
33 typedef volatile unsigned char FLASH_PORT_WIDTHV;
35 #define FPW FLASH_PORT_WIDTH
36 #define FPWV FLASH_PORT_WIDTHV
38 #define CFG_FLASH_CFI_WIDTH FLASH_CFI_8BIT
39 #define CFG_FLASH_NONCFI_WIDTH FLASH_CFI_8BIT
41 /* Intel-compatible flash commands */
42 #define INTEL_PROGRAM 0x00100010
43 #define INTEL_ERASE 0x00200020
44 #define INTEL_WRSETUP 0x00400040
45 #define INTEL_CLEAR 0x00500050
46 #define INTEL_LOCKBIT 0x00600060
47 #define INTEL_PROTECT 0x00010001
48 #define INTEL_STATUS 0x00700070
49 #define INTEL_READID 0x00900090
50 #define INTEL_CFIQRY 0x00980098
51 #define INTEL_SUSERASE 0x00B000B0
52 #define INTEL_PROTPROG 0x00C000C0
53 #define INTEL_CONFIRM 0x00D000D0
54 #define INTEL_WRBLK 0x00e800e8
55 #define INTEL_RESET 0x00FF00FF
57 /* Intel-compatible flash status bits */
58 #define INTEL_FINISHED 0x00800080
59 #define INTEL_OK 0x00800080
60 #define INTEL_ERASESUS 0x00600060
61 #define INTEL_WSM_SUS (INTEL_FINISHED | INTEL_ERASESUS)
63 /* 28F160C3B CFI Data offset - This could vary */
64 #define INTEL_CFI_MFG 0x00 /* Manufacturer ID */
65 #define INTEL_CFI_PART 0x01 /* Product ID */
66 #define INTEL_CFI_LOCK 0x02 /* */
67 #define INTEL_CFI_TWPRG 0x1F /* Typical Single Word Program Timeout 2^n us */
68 #define INTEL_CFI_MBUFW 0x20 /* Typical Max Buffer Write Timeout 2^n us */
69 #define INTEL_CFI_TERB 0x21 /* Typical Block Erase Timeout 2^n ms */
70 #define INTEL_CFI_MWPRG 0x23 /* Maximum Word program timeout 2^n us */
71 #define INTEL_CFI_MERB 0x25 /* Maximum Block Erase Timeout 2^n s */
72 #define INTEL_CFI_SIZE 0x27 /* Device size 2^n bytes */
73 #define INTEL_CFI_CAP 0x28
74 #define INTEL_CFI_WRBUF 0x2A
75 #define INTEL_CFI_BANK 0x2C /* Number of Bank */
76 #define INTEL_CFI_BLK1A 0x2D /* Number of Blocks */
77 #define INTEL_CFI_BLK1B 0x2E /* Number of Blocks */
78 #define INTEL_CFI_SZ1A 0x2F /* Block Region Size */
79 #define INTEL_CFI_SZ1B 0x30
80 #define INTEL_CFI_BLK2A 0x31
81 #define INTEL_CFI_BLK2B 0x32
82 #define INTEL_CFI_SZ2A 0x33
83 #define INTEL_CFI_SZ2B 0x34
85 #define FLASH_CYCLE1 0x0555
86 #define FLASH_CYCLE2 0x0aaa
90 /* not in the flash.h yet */
91 #define FLASH_28F64P30T 0x00B9 /* Intel 28F64P30T ( 64M) */
92 #define FLASH_28F64P30B 0x00BA /* Intel 28F64P30B ( 64M) */
93 #define FLASH_28F128P30T 0x00BB /* Intel 28F128P30T ( 128M = 8M x 16 ) */
94 #define FLASH_28F128P30B 0x00BC /* Intel 28F128P30B ( 128M = 8M x 16 ) */
95 #define FLASH_28F256P30T 0x00BD /* Intel 28F256P30T ( 256M = 16M x 16 ) */
96 #define FLASH_28F256P30B 0x00BE /* Intel 28F256P30B ( 256M = 16M x 16 ) */
98 #define SYNC __asm__("nop")
100 /*-----------------------------------------------------------------------
104 ulong flash_get_size(FPWV * addr, flash_info_t * info);
105 int flash_get_offsets(ulong base, flash_info_t * info);
106 int flash_cmd_rd(volatile u16 * addr, int index);
107 int write_data(flash_info_t * info, ulong dest, FPW data);
108 int write_data_block(flash_info_t * info, ulong src, ulong dest);
109 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data);
110 void inline spin_wheel(void);
111 void flash_sync_real_protect(flash_info_t * info);
112 uchar intel_sector_protected(flash_info_t * info, ushort sector);
114 flash_info_t flash_info[CFG_MAX_FLASH_BANKS];
116 ulong flash_init(void)
122 for (i = 0; i < CFG_MAX_FLASH_BANKS; i++) {
123 memset(&flash_info[i], 0, sizeof(flash_info_t));
127 fbase = (ulong) CFG_FLASH0_BASE;
130 fbase = (ulong) CFG_FLASH1_BASE;
134 flash_get_size((FPWV *) fbase, &flash_info[i]);
135 flash_get_offsets((ulong) fbase, &flash_info[i]);
136 fbase += flash_info[i].size;
137 size += flash_info[i].size;
139 /* get the h/w and s/w protection status in sync */
140 flash_sync_real_protect(&flash_info[i]);
143 /* Protect monitor and environment sectors */
144 flash_protect(FLAG_PROTECT_SET,
146 CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[0]);
151 int flash_get_offsets(ulong base, flash_info_t * info)
154 int sectors, bs, banks;
157 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_ATM) {
158 int sect[] = CFG_ATMEL_SECT;
159 int sectsz[] = CFG_ATMEL_SECTSZ;
161 info->start[0] = base;
162 for (k = 0, i = 0; i < CFG_ATMEL_REGION; i++) {
163 for (j = 0; j < sect[i]; j++, k++) {
164 info->start[k + 1] = info->start[k] + sectsz[i];
165 info->protect[k] = 0;
170 if ((info->flash_id & FLASH_VENDMASK) == FLASH_MAN_INTEL) {
171 volatile u16 *addr16 = (volatile u16 *)base;
173 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
174 *addr16 = (FPW) INTEL_READID;
176 banks = addr16[INTEL_CFI_BANK] & 0xff;
179 info->start[0] = base;
181 for (k = 0, i = 0; i < banks; i++) {
182 /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
183 * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
184 * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
186 bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
187 | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
190 (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
192 for (j = 0; j < sectors; j++, k++) {
193 info->start[k + 1] = info->start[k] + bs;
197 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
203 void flash_print_info(flash_info_t * info)
207 switch (info->flash_id & FLASH_VENDMASK) {
208 case FLASH_MAN_INTEL:
215 printf("Unknown Vendor ");
219 switch (info->flash_id & FLASH_TYPEMASK) {
221 printf("AT49BV040A\n");
223 case FLASH_28F128J3A:
224 printf("Intel 28F128J3A\n");
227 printf("Unknown Chip Type\n");
231 if (info->size > 0x100000) {
234 printf(" Size: %ld", info->size >> 20);
236 remainder = (info->size % 0x100000);
239 remainder = (int)((float)
240 (((float)remainder / (float)1024) *
242 printf(".%d ", remainder);
245 printf("MB in %d Sectors\n", info->sector_count);
247 printf(" Size: %ld KB in %d Sectors\n",
248 info->size >> 10, info->sector_count);
250 printf(" Sector Start Addresses:");
251 for (i = 0; i < info->sector_count; ++i) {
255 info->start[i], info->protect[i] ? " (RO)" : " ");
261 * The following code cannot be run from FLASH!
263 ulong flash_get_size(FPWV * addr, flash_info_t * info)
265 volatile u16 *addr16 = (volatile u16 *)addr;
266 int intel = 0, banks = 0;
270 addr[FLASH_CYCLE1] = (FPWV) 0x00AA00AA; /* for Atmel, Intel ignores this */
271 addr[FLASH_CYCLE2] = (FPWV) 0x00550055; /* for Atmel, Intel ignores this */
272 addr[FLASH_CYCLE1] = (FPWV) 0x00900090; /* selects Intel or Atmel */
274 switch (addr[0] & 0xff) {
275 case (u8) ATM_MANUFACT:
276 info->flash_id = FLASH_MAN_ATM;
279 case (u8) INTEL_MANUFACT:
280 /* Terminate Atmel ID read */
281 addr[0] = (FPWV) 0x00F000F0;
282 /* Write auto select command: read Manufacturer ID */
283 /* Write auto select command sequence and test FLASH answer */
284 *addr16 = (FPW) INTEL_RESET; /* restore read mode */
285 *addr16 = (FPW) INTEL_READID;
287 info->flash_id = FLASH_MAN_INTEL;
288 value = (addr16[INTEL_CFI_MFG] << 8);
289 value |= addr16[INTEL_CFI_PART] & 0xff;
293 printf("Unknown Flash\n");
294 info->flash_id = FLASH_UNKNOWN;
295 info->sector_count = 0;
298 *addr = (FPW) 0x00F000F0;
299 *addr = (FPW) INTEL_RESET; /* restore read mode */
300 return (0); /* no or unknown flash */
304 case (u8) ATM_ID_LV040:
305 info->flash_id += FLASH_AT040;
307 case (u16) INTEL_ID_28F128J3:
308 info->flash_id += FLASH_28F128J3A;
310 case (u16) INTEL_ID_28F64P30T:
311 info->flash_id += FLASH_28F64P30T;
313 case (u16) INTEL_ID_28F64P30B:
314 info->flash_id += FLASH_28F64P30B;
316 case (u16) INTEL_ID_28F128P30T:
317 info->flash_id += FLASH_28F128P30T;
319 case (u16) INTEL_ID_28F128P30B:
320 info->flash_id += FLASH_28F128P30B;
322 case (u16) INTEL_ID_28F256P30T:
323 info->flash_id += FLASH_28F256P30T;
325 case (u16) INTEL_ID_28F256P30B:
326 info->flash_id += FLASH_28F256P30B;
329 info->flash_id = FLASH_UNKNOWN;
334 /* Intel spec. under CFI section */
338 banks = addr16[INTEL_CFI_BANK] & 0xff;
341 for (i = 0; i < banks; i++) {
342 /* Geometry y1 = y1 + 1, y2 = y2 + 1, CFI spec.
343 * To be exact, Z = [0x2f 0x30] (LE) * 256 bytes * [0x2D 0x2E] block count
344 * Z = [0x33 0x34] (LE) * 256 bytes * [0x31 0x32] block count
346 bs = ((((addr16[INTEL_CFI_SZ1B + (i * 4)] & 0xff) << 8)
347 | (addr16[INTEL_CFI_SZ1A + (i * 4)] & 0xff)) *
350 (addr16[INTEL_CFI_BLK1A + (i * 4)] & 0xff) + 1;
351 sz += (bs * sectors);
354 info->sector_count = sectors;
356 *addr = (FPW) INTEL_RESET; /* restore read mode */
358 int sect[] = CFG_ATMEL_SECT;
359 int sectsz[] = CFG_ATMEL_SECTSZ;
361 info->sector_count = 0;
363 for (i = 0; i < CFG_ATMEL_REGION; i++) {
364 info->sector_count += sect[i];
365 info->size += sect[i] * sectsz[i];
369 addr[0] = (FPWV) 0x00F000F0;
372 if (info->sector_count > CFG_MAX_FLASH_SECT) {
373 printf("** ERROR: sector count %d > max (%d) **\n",
374 info->sector_count, CFG_MAX_FLASH_SECT);
375 info->sector_count = CFG_MAX_FLASH_SECT;
381 int flash_cmd_rd(volatile u16 * addr, int index)
383 return (int)addr[index];
387 * This function gets the u-boot flash sector protection status
388 * (flash_info_t.protect[]) in sync with the sector protection
389 * status stored in hardware.
391 void flash_sync_real_protect(flash_info_t * info)
395 switch (info->flash_id & FLASH_TYPEMASK) {
396 case FLASH_28F160C3B:
397 case FLASH_28F160C3T:
398 case FLASH_28F320C3B:
399 case FLASH_28F320C3T:
400 case FLASH_28F640C3B:
401 case FLASH_28F640C3T:
402 for (i = 0; i < info->sector_count; ++i) {
403 info->protect[i] = intel_sector_protected(info, i);
407 /* no h/w protect support */
413 * checks if "sector" in bank "info" is protected. Should work on intel
414 * strata flash chips 28FxxxJ3x in 8-bit mode.
415 * Returns 1 if sector is protected (or timed-out while trying to read
416 * protection status), 0 if it is not.
418 uchar intel_sector_protected(flash_info_t * info, ushort sector)
421 FPWV *lock_conf_addr;
426 * first, wait for the WSM to be finished. The rationale for
427 * waiting for the WSM to become idle for at most
428 * CFG_FLASH_ERASE_TOUT is as follows. The WSM can be busy
429 * because of: (1) erase, (2) program or (3) lock bit
430 * configuration. So we just wait for the longest timeout of
431 * the (1)-(3), i.e. the erase timeout.
434 /* wait at least 35ns (W12) before issuing Read Status Register */
436 addr = (FPWV *) info->start[sector];
437 *addr = (FPW) INTEL_STATUS;
439 start = get_timer(0);
440 while ((*addr & (FPW) INTEL_FINISHED) != (FPW) INTEL_FINISHED) {
441 if (get_timer(start) > CFG_FLASH_UNLOCK_TOUT) {
442 *addr = (FPW) INTEL_RESET; /* restore read mode */
443 printf("WSM busy too long, can't get prot status\n");
448 /* issue the Read Identifier Codes command */
449 *addr = (FPW) INTEL_READID;
451 /* Intel example code uses offset of 4 for 8-bit flash */
452 lock_conf_addr = (FPWV *) info->start[sector];
453 ret = (lock_conf_addr[INTEL_CFI_LOCK] & (FPW) INTEL_PROTECT) ? 1 : 0;
455 /* put flash back in read mode */
456 *addr = (FPW) INTEL_RESET;
461 int flash_erase(flash_info_t * info, int s_first, int s_last)
463 int flag, prot, sect;
464 ulong type, start, last;
465 int rcode = 0, intel = 0;
467 if ((s_first < 0) || (s_first > s_last)) {
468 if (info->flash_id == FLASH_UNKNOWN)
469 printf("- missing\n");
471 printf("- no sectors to erase\n");
475 type = (info->flash_id & FLASH_VENDMASK);
477 if (type != (FLASH_MAN_INTEL & FLASH_VENDMASK)) {
478 if (type != (FLASH_MAN_ATM & FLASH_VENDMASK)) {
479 type = (info->flash_id & FLASH_VENDMASK);
481 ("Can't erase unknown flash type %08lx - aborted\n",
487 if (type == FLASH_MAN_INTEL)
491 for (sect = s_first; sect <= s_last; ++sect) {
492 if (info->protect[sect]) {
498 printf("- Warning: %d protected sectors will not be erased!\n",
503 start = get_timer(0);
506 /* Start erase on unprotected sectors */
507 for (sect = s_first; sect <= s_last; sect++) {
508 if (info->protect[sect] == 0) { /* not protected */
510 FPWV *addr = (FPWV *) (info->start[sect]);
515 /* arm simple, non interrupt dependent timer */
516 start = get_timer(0);
519 *addr = (FPW) INTEL_READID;
520 min = addr[INTEL_CFI_TERB] & 0xff;
521 min = 1 << min; /* ms */
522 min = (min / info->sector_count) * 1000;
524 /* start erase block */
525 *addr = (FPW) INTEL_CLEAR; /* clear status register */
526 *addr = (FPW) INTEL_ERASE; /* erase setup */
527 *addr = (FPW) INTEL_CONFIRM; /* erase confirm */
529 while ((*addr & (FPW) INTEL_FINISHED) !=
530 (FPW) INTEL_FINISHED) {
532 if (get_timer(start) >
533 CFG_FLASH_ERASE_TOUT) {
535 *addr = (FPW) INTEL_SUSERASE; /* suspend erase */
536 *addr = (FPW) INTEL_RESET; /* reset to read mode */
543 *addr = (FPW) INTEL_RESET; /* resest to read mode */
545 FPWV *base; /* first address in bank */
548 flag = disable_interrupts();
550 atmeladdr = (FPWV *) addr; /* concatenate to 8 bit */
551 base = (FPWV *) (CFG_ATMEL_BASE); /* First sector */
553 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
554 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
555 base[FLASH_CYCLE1] = (u8) 0x00800080; /* erase mode */
556 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
557 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
558 *atmeladdr = (u8) 0x00300030; /* erase sector */
563 while ((*atmeladdr & (u8) 0x00800080) !=
565 if (get_timer(start) >
566 CFG_FLASH_ERASE_TOUT) {
568 *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
575 *atmeladdr = (u8) 0x00F000F0; /* reset to read mode */
576 } /* Atmel or Intel */
584 int write_buff(flash_info_t * info, uchar * src, ulong addr, ulong cnt)
586 if (info->flash_id == FLASH_UNKNOWN)
589 switch (info->flash_id & FLASH_VENDMASK) {
593 int bytes; /* number of bytes to program in current word */
594 int left; /* number of bytes left to program */
597 for (left = cnt, res = 0;
598 left > 0 && res == 0;
599 addr += sizeof(data), left -=
600 sizeof(data) - bytes) {
602 bytes = addr & (sizeof(data) - 1);
603 addr &= ~(sizeof(data) - 1);
605 /* combine source and destination data so can program
606 * an entire word of 16 or 32 bits
608 for (i = 0; i < sizeof(data); i++) {
610 if (i < bytes || i - bytes >= left)
611 data += *((uchar *) addr + i);
616 data = (data >> 8) | (data << 8);
617 res = write_word_atm(info, (FPWV *) addr, data);
620 } /* case FLASH_MAN_ATM */
622 case FLASH_MAN_INTEL:
626 int count, i, l, rc, port_width;
628 /* get lower word aligned address */
630 port_width = sizeof(FPW);
633 * handle unaligned start bytes
635 if ((l = addr - wp) != 0) {
637 for (i = 0, cp = wp; i < l; ++i, ++cp) {
638 data = (data << 8) | (*(uchar *) cp);
641 for (; i < port_width && cnt > 0; ++i) {
642 data = (data << 8) | *src++;
647 for (; cnt == 0 && i < port_width; ++i, ++cp)
648 data = (data << 8) | (*(uchar *) cp);
650 if ((rc = write_data(info, wp, data)) != 0)
656 if (cnt > WR_BLOCK) {
658 * handle word aligned part
661 while (cnt >= WR_BLOCK) {
664 write_data_block(info,
673 if (count++ > 0x800) {
680 /* handle word aligned part */
681 if (cnt < WR_BLOCK) {
683 * handle word aligned part
686 while (cnt >= port_width) {
688 for (i = 0; i < port_width; ++i)
689 data = (data << 8) | *src++;
693 (ulong) ((FPWV *) wp),
699 if (count++ > 0x800) {
710 * handle unaligned tail bytes
713 for (i = 0, cp = wp; i < port_width && cnt > 0;
715 data = (data << 8) | (*src++);
718 for (; i < port_width; ++i, ++cp) {
719 data = (data << 8) | (*(uchar *) cp);
722 return write_data(info, (ulong) ((FPWV *) wp),
725 } /* case FLASH_MAN_INTEL */
732 /*-----------------------------------------------------------------------
733 * Write a word or halfword to Flash, returns:
736 * 2 - Flash not erased
738 int write_data_block(flash_info_t * info, ulong src, ulong dest)
740 FPWV *srcaddr = (FPWV *) src;
741 FPWV *dstaddr = (FPWV *) dest;
745 /* Check if Flash is (sufficiently) erased */
746 for (i = 0; i < WR_BLOCK; i++)
747 if ((*dstaddr++ & 0xff) != 0xff) {
748 printf("not erased at %08lx (%lx)\n",
749 (ulong) dstaddr, *dstaddr);
753 dstaddr = (FPWV *) dest;
755 /* Disable interrupts which might cause a timeout here */
756 flag = disable_interrupts();
758 *dstaddr = (FPW) INTEL_WRBLK; /* write block setup */
763 /* arm simple, non interrupt dependent timer */
764 start = get_timer(0);
766 /* wait while polling the status register */
767 while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
768 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
769 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
774 *dstaddr = (FPW) WR_BLOCK - 1; /* write 32 to buffer */
775 for (i = 0; i < WR_BLOCK; i++)
776 *dstaddr++ = *srcaddr++;
779 *dstaddr = (FPW) INTEL_CONFIRM; /* write 32 to buffer */
781 /* arm simple, non interrupt dependent timer */
782 start = get_timer(0);
784 /* wait while polling the status register */
785 while ((*dstaddr & (FPW) INTEL_FINISHED) != (FPW) INTEL_OK) {
786 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
787 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
792 *dstaddr = (FPW) INTEL_RESET; /* restore read mode */
797 /*-----------------------------------------------------------------------
798 * Write a word or halfword to Flash, returns:
801 * 2 - Flash not erased
803 int write_data(flash_info_t * info, ulong dest, FPW data)
805 FPWV *addr = (FPWV *) dest;
809 /* Check if Flash is (sufficiently) erased */
810 if ((*addr & data) != data) {
811 printf("not erased at %08lx (%lx)\n", (ulong) addr,
816 /* Disable interrupts which might cause a timeout here */
817 flag = (int)disable_interrupts();
819 *addr = (FPW) INTEL_CLEAR;
820 *addr = (FPW) INTEL_RESET;
822 *addr = (FPW) INTEL_WRSETUP; /* write setup */
828 /* arm simple, non interrupt dependent timer */
829 start = get_timer(0);
831 /* wait while polling the status register */
832 while ((*addr & (FPW) INTEL_OK) != (FPW) INTEL_OK) {
833 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
834 *addr = (FPW) INTEL_SUSERASE; /* suspend mode */
835 *addr = (FPW) INTEL_CLEAR; /* clear status */
836 *addr = (FPW) INTEL_RESET; /* reset */
841 *addr = (FPW) INTEL_CLEAR; /* clear status */
842 *addr = (FPW) INTEL_RESET; /* restore read mode */
847 /*-----------------------------------------------------------------------
848 * Write a word to Flash for ATMEL FLASH
849 * A word is 16 bits, whichever the bus width of the flash bank
850 * (not an individual chip) is.
855 * 2 - Flash not erased
857 int write_word_atm(flash_info_t * info, volatile u8 * dest, u16 data)
861 int res = 0; /* result, assume success */
862 FPWV *base; /* first address in flash bank */
864 /* Check if Flash is (sufficiently) erased */
865 if ((*((volatile u16 *)dest) & data) != data) {
869 base = (FPWV *) (CFG_ATMEL_BASE);
871 for (i = 0; i < sizeof(u16); i++) {
872 /* Disable interrupts which might cause a timeout here */
873 flag = disable_interrupts();
875 base[FLASH_CYCLE1] = (u8) 0x00AA00AA; /* unlock */
876 base[FLASH_CYCLE2] = (u8) 0x00550055; /* unlock */
877 base[FLASH_CYCLE1] = (u8) 0x00A000A0; /* selects program mode */
879 *dest = data; /* start programming the data */
881 /* re-enable interrupts if necessary */
885 start = get_timer(0);
887 /* data polling for D7 */
889 && (*dest & (u8) 0x00800080) !=
890 (data & (u8) 0x00800080)) {
891 if (get_timer(start) > CFG_FLASH_WRITE_TOUT) {
892 *dest = (u8) 0x00F000F0; /* reset bank */
897 *dest++ = (u8) 0x00F000F0; /* reset bank */
904 void inline spin_wheel(void)
907 static char w[] = "\\/-";
909 printf("\010%c", w[p]);
910 (++p == 3) ? (p = 0) : 0;
913 #ifdef CFG_FLASH_PROTECTION
914 /*-----------------------------------------------------------------------
916 int flash_real_protect(flash_info_t * info, long sector, int prot)
918 int rcode = 0; /* assume success */
919 FPWV *addr; /* address of sector */
922 addr = (FPWV *) (info->start[sector]);
924 switch (info->flash_id & FLASH_TYPEMASK) {
925 case FLASH_28F160C3B:
926 case FLASH_28F160C3T:
927 case FLASH_28F320C3B:
928 case FLASH_28F320C3T:
929 case FLASH_28F640C3B:
930 case FLASH_28F640C3T:
931 *addr = (FPW) INTEL_RESET; /* make sure in read mode */
932 *addr = (FPW) INTEL_LOCKBIT; /* lock command setup */
935 *addr = (FPW) INTEL_PROTECT; /* lock sector */
937 *addr = (FPW) INTEL_CONFIRM; /* unlock sector */
939 /* now see if it really is locked/unlocked as requested */
940 *addr = (FPW) INTEL_READID;
942 /* read sector protection at sector address, (A7 .. A0) = 0x02.
943 * D0 = 1 for each device if protected.
944 * If at least one device is protected the sector is marked
945 * protected, but return failure. Mixed protected and
946 * unprotected devices within a sector should never happen.
948 value = addr[2] & (FPW) INTEL_PROTECT;
950 info->protect[sector] = 0;
951 else if (value == (FPW) INTEL_PROTECT)
952 info->protect[sector] = 1;
954 /* error, mixed protected and unprotected */
956 info->protect[sector] = 1;
958 if (info->protect[sector] != prot)
959 rcode = 1; /* failed to protect/unprotect as requested */
961 /* reload all protection bits from hardware for now */
962 flash_sync_real_protect(info);
966 /* no hardware protect that we support */
967 info->protect[sector] = prot;