2 * (C) Copyright 2000-2003
3 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
5 * Copyright (C) 2004-2007, 2012 Freescale Semiconductor, Inc.
6 * Hayden Fraser (Hayden.Fraser@freescale.com)
8 * See file CREDITS for list of people who contributed to this
11 * This program is free software; you can redistribute it and/or
12 * modify it under the terms of the GNU General Public License as
13 * published by the Free Software Foundation; either version 2 of
14 * the License, or (at your option) any later version.
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
19 * GNU General Public License for more details.
21 * You should have received a copy of the GNU General Public License
22 * along with this program; if not, write to the Free Software
23 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
28 #include <asm/immap.h>
35 puts("Freescale MCF5253 DEMO\n");
39 phys_size_t initdram(int board_type)
44 * Check to see if the SDRAM has already been initialized
45 * by a run control tool
47 if (!(mbar_readLong(MCFSIM_DCR) & 0x8000)) {
50 RC = (CONFIG_SYS_CLK / 1000000) >> 1;
53 /* Initialize DRAM Control Register: DCR */
54 mbar_writeShort(MCFSIM_DCR, (0x8400 | RC));
57 mbar_writeLong(MCFSIM_DACR0, 0x00003224);
61 dramsize = (CONFIG_SYS_SDRAM_SIZE << 20);
62 temp = (dramsize - 1) & 0xFFFC0000;
63 mbar_writeLong(MCFSIM_DMR0, temp | 1);
66 mbar_writeLong(MCFSIM_DACR0, 0x0000322c);
70 /* Write to this block to initiate precharge */
71 *(u32 *) (CONFIG_SYS_SDRAM_BASE) = 0xa5a5a5a5;
75 /* Set RE bit in DACR */
76 mbar_writeLong(MCFSIM_DACR0,
77 mbar_readLong(MCFSIM_DACR0) | 0x8000);
80 /* Wait for at least 8 auto refresh cycles to occur */
83 /* Finish the configuration by issuing the MRS */
84 mbar_writeLong(MCFSIM_DACR0,
85 mbar_readLong(MCFSIM_DACR0) | 0x0040);
88 *(u32 *) (CONFIG_SYS_SDRAM_BASE + 0x800) = 0xa5a5a5a5;
97 /* TODO: XXX XXX XXX */
98 printf("DRAM test not implemented!\n");
103 #ifdef CONFIG_CMD_IDE
105 int ide_preinit(void)
110 void ide_set_reset(int idereset)
112 atac_t *ata = (atac_t *) CONFIG_SYS_ATA_BASE_ADDR;
114 /* t1, t2, t3, t4, t5, t6, t9, tRD, tA */
115 int piotms[5][9] = { {70, 165, 60, 30, 50, 5, 20, 0, 35}, /* PIO 0 */
116 {50, 125, 45, 20, 35, 5, 15, 0, 35}, /* PIO 1 */
117 {30, 100, 30, 15, 20, 5, 10, 0, 35}, /* PIO 2 */
118 {30, 80, 30, 10, 20, 5, 10, 0, 35}, /* PIO 3 */
119 {25, 70, 20, 10, 20, 5, 10, 0, 35} /* PIO 4 */
127 mbar2_writeLong(CIM_MISCCR, CIM_MISCCR_CPUEND);
129 #define CALC_TIMING(t) (t + period - 1) / period
130 period = 1000000000 / (CONFIG_SYS_CLK / 2); /* period in ns */
132 /*ata->ton = CALC_TIMING (180); */
133 out_8(&ata->t1, CALC_TIMING(piotms[2][0]));
134 out_8(&ata->t2w, CALC_TIMING(piotms[2][1]));
135 out_8(&ata->t2r, CALC_TIMING(piotms[2][1]));
136 out_8(&ata->ta, CALC_TIMING(piotms[2][8]));
137 out_8(&ata->trd, CALC_TIMING(piotms[2][7]));
138 out_8(&ata->t4, CALC_TIMING(piotms[2][3]));
139 out_8(&ata->t9, CALC_TIMING(piotms[2][6]));
142 out_8(&ata->cr, 0x40);
145 setbits_8(&ata->cr, 0x01);
148 #endif /* CONFIG_CMD_IDE */
151 #ifdef CONFIG_DRIVER_DM9000
152 int board_eth_init(bd_t *bis)
154 return dm9000_initialize(bis);