board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <dm/platform_data/serial_pl01x.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <fsl-mc/fsl_mc.h>
  20 #include <env_internal.h>
  21 #include <efi_loader.h>
  22 #include <asm/arch/mmu.h>
  23 #include <hwconfig.h>
  24 #include <asm/arch/clock.h>
  25 #include <asm/arch/config.h>
  26 #include <asm/arch/fsl_serdes.h>
  27 #include <asm/arch/soc.h>
  28 #include "../common/qixis.h"
  29 #include "../common/vid.h"
  30 #include <fsl_immap.h>
  31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  32 #include <asm/gic-v3.h>
  33 #include <cpu_func.h>
  34
  35 #ifdef CONFIG_EMC2305
  36 #include "../common/emc2305.h"
  37 #endif
  38
  39 #define GIC_LPI_SIZE                             0x200000
  40 #ifdef CONFIG_TARGET_LX2160AQDS
  41 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  42 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  43 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  44 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  45 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  46 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  47 #define SDHC1_BASE_PMUX_DSPI                    2
  48 #define SDHC2_BASE_PMUX_DSPI                    2
  49 #define IIC5_PMUX_SPI3                          3
  50 #endif /* CONFIG_TARGET_LX2160AQDS */
  51
  52 DECLARE_GLOBAL_DATA_PTR;
  53
  54 static struct pl01x_serial_platdata serial0 = {
  55 #if CONFIG_CONS_INDEX == 0
  56         .base = CONFIG_SYS_SERIAL0,
  57 #elif CONFIG_CONS_INDEX == 1
  58         .base = CONFIG_SYS_SERIAL1,
  59 #else
  60 #error "Unsupported console index value."
  61 #endif
  62         .type = TYPE_PL011,
  63 };
  64
  65 U_BOOT_DEVICE(nxp_serial0) = {
  66         .name = "serial_pl01x",
  67         .platdata = &serial0,
  68 };
  69
  70 static struct pl01x_serial_platdata serial1 = {
  71         .base = CONFIG_SYS_SERIAL1,
  72         .type = TYPE_PL011,
  73 };
  74
  75 U_BOOT_DEVICE(nxp_serial1) = {
  76         .name = "serial_pl01x",
  77         .platdata = &serial1,
  78 };
  79
  80 int select_i2c_ch_pca9547(u8 ch)
  81 {
  82         int ret;
  83
  84 #ifndef CONFIG_DM_I2C
  85         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  86 #else
  87         struct udevice *dev;
  88
  89         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  90         if (!ret)
  91                 ret = dm_i2c_write(dev, 0, &ch, 1);
  92 #endif
  93         if (ret) {
  94                 puts("PCA: failed to select proper channel\n");
  95                 return ret;
  96         }
  97
  98         return 0;
  99 }
 100
 101 static void uart_get_clock(void)
 102 {
 103         serial0.clock = get_serial_clock();
 104         serial1.clock = get_serial_clock();
 105 }
 106
 107 int board_early_init_f(void)
 108 {
 109 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 110         i2c_early_init_f();
 111 #endif
 112         /* get required clock for UART IP */
 113         uart_get_clock();
 114
 115 #ifdef CONFIG_EMC2305
 116         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 117         emc2305_init();
 118         set_fan_speed(I2C_EMC2305_PWM);
 119         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 120 #endif
 121
 122         fsl_lsch3_early_init_f();
 123         return 0;
 124 }
 125
 126 #ifdef CONFIG_OF_BOARD_FIXUP
 127 int board_fix_fdt(void *fdt)
 128 {
 129         char *reg_names, *reg_name;
 130         int names_len, old_name_len, new_name_len, remaining_names_len;
 131         struct str_map {
 132                 char *old_str;
 133                 char *new_str;
 134         } reg_names_map[] = {
 135                 { "ccsr", "dbi" },
 136                 { "pf_ctrl", "ctrl" }
 137         };
 138         int off = -1, i = 0;
 139
 140         if (IS_SVR_REV(get_svr(), 1, 0))
 141                 return 0;
 142
 143         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 144         while (off != -FDT_ERR_NOTFOUND) {
 145                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 146                             strlen("fsl,ls-pcie") + 1);
 147
 148                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 149                                                 &names_len);
 150                 if (!reg_names)
 151                         continue;
 152
 153                 reg_name = reg_names;
 154                 remaining_names_len = names_len - (reg_name - reg_names);
 155                 i = 0;
 156                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 157                         old_name_len = strlen(reg_names_map[i].old_str);
 158                         new_name_len = strlen(reg_names_map[i].new_str);
 159                         if (memcmp(reg_name, reg_names_map[i].old_str,
 160                                    old_name_len) == 0) {
 161                                 /* first only leave required bytes for new_str
 162                                  * and copy rest of the string after it
 163                                  */
 164                                 memcpy(reg_name + new_name_len,
 165                                        reg_name + old_name_len,
 166                                        remaining_names_len - old_name_len);
 167                                 /* Now copy new_str */
 168                                 memcpy(reg_name, reg_names_map[i].new_str,
 169                                        new_name_len);
 170                                 names_len -= old_name_len;
 171                                 names_len += new_name_len;
 172                                 i++;
 173                         }
 174
 175                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 176                         if (!reg_name)
 177                                 break;
 178
 179                         reg_name += 1;
 180
 181                         remaining_names_len = names_len -
 182                                               (reg_name - reg_names);
 183                 }
 184
 185                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 186                 off = fdt_node_offset_by_compatible(fdt, off,
 187                                                     "fsl,lx2160a-pcie");
 188         }
 189
 190         return 0;
 191 }
 192 #endif
 193
 194 #if defined(CONFIG_TARGET_LX2160AQDS)
 195 void esdhc_dspi_status_fixup(void *blob)
 196 {
 197         const char esdhc0_path[] = "/soc/esdhc@2140000";
 198         const char esdhc1_path[] = "/soc/esdhc@2150000";
 199         const char dspi0_path[] = "/soc/spi@2100000";
 200         const char dspi1_path[] = "/soc/spi@2110000";
 201         const char dspi2_path[] = "/soc/spi@2120000";
 202
 203         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 204         u32 sdhc1_base_pmux;
 205         u32 sdhc2_base_pmux;
 206         u32 iic5_pmux;
 207
 208         /* Check RCW field sdhc1_base_pmux to enable/disable
 209          * esdhc0/dspi0 DT node
 210          */
 211         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 212                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 213         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 214
 215         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 216                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 217                                  sizeof("okay"), 1);
 218                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 219                                  sizeof("disabled"), 1);
 220         } else {
 221                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 222                                  sizeof("okay"), 1);
 223                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 224                                  sizeof("disabled"), 1);
 225         }
 226
 227         /* Check RCW field sdhc2_base_pmux to enable/disable
 228          * esdhc1/dspi1 DT node
 229          */
 230         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 231                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 232         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 233
 234         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 235                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 236                                  sizeof("okay"), 1);
 237                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 238                                  sizeof("disabled"), 1);
 239         } else {
 240                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 241                                  sizeof("okay"), 1);
 242                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 243                                  sizeof("disabled"), 1);
 244         }
 245
 246         /* Check RCW field IIC5 to enable dspi2 DT node */
 247         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 248                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 249         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 250
 251         if (iic5_pmux == IIC5_PMUX_SPI3)
 252                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 253                                  sizeof("okay"), 1);
 254         else
 255                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 256                                  sizeof("disabled"), 1);
 257 }
 258 #endif
 259
 260 int esdhc_status_fixup(void *blob, const char *compat)
 261 {
 262 #if defined(CONFIG_TARGET_LX2160AQDS)
 263         /* Enable esdhc and dspi DT nodes based on RCW fields */
 264         esdhc_dspi_status_fixup(blob);
 265 #else
 266         /* Enable both esdhc DT nodes for LX2160ARDB */
 267         do_fixup_by_compat(blob, compat, "status", "okay",
 268                            sizeof("okay"), 1);
 269 #endif
 270         return 0;
 271 }
 272
 273 #if defined(CONFIG_VID)
 274 int i2c_multiplexer_select_vid_channel(u8 channel)
 275 {
 276         return select_i2c_ch_pca9547(channel);
 277 }
 278
 279 int init_func_vid(void)
 280 {
 281         if (adjust_vdd(0) < 0)
 282                 printf("core voltage not adjusted\n");
 283
 284         return 0;
 285 }
 286 #endif
 287
 288 int checkboard(void)
 289 {
 290         enum boot_src src = get_boot_src();
 291         char buf[64];
 292         u8 sw;
 293 #ifdef CONFIG_TARGET_LX2160AQDS
 294         int clock;
 295         static const char *const freq[] = {"100", "125", "156.25",
 296                                            "161.13", "322.26", "", "", "",
 297                                            "", "", "", "", "", "", "",
 298                                            "100 separate SSCG"};
 299 #endif
 300
 301         cpu_name(buf);
 302 #ifdef CONFIG_TARGET_LX2160AQDS
 303         printf("Board: %s-QDS, ", buf);
 304 #else
 305         printf("Board: %s-RDB, ", buf);
 306 #endif
 307
 308         sw = QIXIS_READ(arch);
 309         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 310
 311         if (src == BOOT_SOURCE_SD_MMC) {
 312                 puts("SD\n");
 313         } else if (src == BOOT_SOURCE_SD_MMC2) {
 314                 puts("eMMC\n");
 315         } else {
 316                 sw = QIXIS_READ(brdcfg[0]);
 317                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 318                 switch (sw) {
 319                 case 0:
 320                 case 4:
 321                         puts("FlexSPI DEV#0\n");
 322                         break;
 323                 case 1:
 324                         puts("FlexSPI DEV#1\n");
 325                         break;
 326                 case 2:
 327                 case 3:
 328                         puts("FlexSPI EMU\n");
 329                         break;
 330                 default:
 331                         printf("invalid setting, xmap: %d\n", sw);
 332                         break;
 333                 }
 334         }
 335 #ifdef CONFIG_TARGET_LX2160AQDS
 336         printf("FPGA: v%d (%s), build %d",
 337                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 338                (int)qixis_read_minor());
 339         /* the timestamp string contains "\n" at the end */
 340         printf(" on %s", qixis_read_time(buf));
 341
 342         puts("SERDES1 Reference : ");
 343         sw = QIXIS_READ(brdcfg[2]);
 344         clock = sw >> 4;
 345         printf("Clock1 = %sMHz ", freq[clock]);
 346         clock = sw & 0x0f;
 347         printf("Clock2 = %sMHz", freq[clock]);
 348
 349         sw = QIXIS_READ(brdcfg[3]);
 350         puts("\nSERDES2 Reference : ");
 351         clock = sw >> 4;
 352         printf("Clock1 = %sMHz ", freq[clock]);
 353         clock = sw & 0x0f;
 354         printf("Clock2 = %sMHz", freq[clock]);
 355
 356         sw = QIXIS_READ(brdcfg[12]);
 357         puts("\nSERDES3 Reference : ");
 358         clock = sw >> 4;
 359         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 360 #else
 361         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 362
 363         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 364         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 365         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 366 #endif
 367         return 0;
 368 }
 369
 370 #ifdef CONFIG_TARGET_LX2160AQDS
 371 /*
 372  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 373  */
 374 u8 qixis_esdhc_detect_quirk(void)
 375 {
 376         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 377          * SDHC1 Card ID:
 378          * Specifies the type of card installed in the SDHC1 adapter slot.
 379          * 000= (reserved)
 380          * 001= eMMC V4.5 adapter is installed.
 381          * 010= SD/MMC 3.3V adapter is installed.
 382          * 011= eMMC V4.4 adapter is installed.
 383          * 100= eMMC V5.0 adapter is installed.
 384          * 101= MMC card/Legacy (3.3V) adapter is installed.
 385          * 110= SDCard V2/V3 adapter installed.
 386          * 111= no adapter is installed.
 387          */
 388         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 389                  QIXIS_ESDHC_NO_ADAPTER);
 390 }
 391
 392 int config_board_mux(void)
 393 {
 394         u8 reg11, reg5, reg13;
 395         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 396         u32 sdhc1_base_pmux;
 397         u32 sdhc2_base_pmux;
 398         u32 iic5_pmux;
 399
 400         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 401          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 402          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 403          * Qixis and remote systems are isolated from the I2C1 bus.
 404          * Processor connections are still available.
 405          * SPI2 CS2_B controls EN25S64 SPI memory device.
 406          * SPI3 CS2_B controls EN25S64 SPI memory device.
 407          * EC2 connects to PHY #2 using RGMII protocol.
 408          * CLK_OUT connects to FPGA for clock measurement.
 409          */
 410
 411         reg5 = QIXIS_READ(brdcfg[5]);
 412         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 413         QIXIS_WRITE(brdcfg[5], reg5);
 414
 415         /* Check RCW field sdhc1_base_pmux
 416          * esdhc0 : sdhc1_base_pmux = 0
 417          * dspi0  : sdhc1_base_pmux = 2
 418          */
 419         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 420                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 421         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 422
 423         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 424                 reg11 = QIXIS_READ(brdcfg[11]);
 425                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 426                 QIXIS_WRITE(brdcfg[11], reg11);
 427         } else {
 428                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 429                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 430                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 431                  */
 432                 reg11 = QIXIS_READ(brdcfg[11]);
 433                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 434                 QIXIS_WRITE(brdcfg[11], reg11);
 435         }
 436
 437         /* Check RCW field sdhc2_base_pmux
 438          * esdhc1 : sdhc2_base_pmux = 0 (default)
 439          * dspi1  : sdhc2_base_pmux = 2
 440          */
 441         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 442                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 443         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 444
 445         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 446                 reg13 = QIXIS_READ(brdcfg[13]);
 447                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 448                 QIXIS_WRITE(brdcfg[13], reg13);
 449         } else {
 450                 reg13 = QIXIS_READ(brdcfg[13]);
 451                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 452                 QIXIS_WRITE(brdcfg[13], reg13);
 453         }
 454
 455         /* Check RCW field IIC5 to enable dspi2 DT nodei
 456          * dspi2: IIC5 = 3
 457          */
 458         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 459                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 460         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 461
 462         if (iic5_pmux == IIC5_PMUX_SPI3) {
 463                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 464                 reg11 = QIXIS_READ(brdcfg[11]);
 465                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 466                 QIXIS_WRITE(brdcfg[11], reg11);
 467
 468                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 469                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 470                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 471                  */
 472                 reg11 = QIXIS_READ(brdcfg[11]);
 473                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 474                 QIXIS_WRITE(brdcfg[11], reg11);
 475         } else {
 476                 /*  Routes {SDHC1_DAT4} to SDHC1 adapter slot */
 477                 reg11 = QIXIS_READ(brdcfg[11]);
 478                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 479                 QIXIS_WRITE(brdcfg[11], reg11);
 480
 481                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 482                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 483                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 484                  */
 485                 reg11 = QIXIS_READ(brdcfg[11]);
 486                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 487                 QIXIS_WRITE(brdcfg[11], reg11);
 488         }
 489
 490         return 0;
 491 }
 492 #elif defined(CONFIG_TARGET_LX2160ARDB)
 493 int config_board_mux(void)
 494 {
 495         u8 brdcfg;
 496
 497         brdcfg = QIXIS_READ(brdcfg[4]);
 498         /* The BRDCFG4 register controls general board configuration.
 499          *|-------------------------------------------|
 500          *|Field  | Function                          |
 501          *|-------------------------------------------|
 502          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 503          *|CAN_EN | 0= CAN transceivers are disabled. |
 504          *|       | 1= CAN transceivers are enabled.  |
 505          *|-------------------------------------------|
 506          */
 507         brdcfg |= BIT_MASK(5);
 508         QIXIS_WRITE(brdcfg[4], brdcfg);
 509
 510         return 0;
 511 }
 512 #else
 513 int config_board_mux(void)
 514 {
 515         return 0;
 516 }
 517 #endif
 518
 519 unsigned long get_board_sys_clk(void)
 520 {
 521 #ifdef CONFIG_TARGET_LX2160AQDS
 522         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 523
 524         switch (sysclk_conf & 0x03) {
 525         case QIXIS_SYSCLK_100:
 526                 return 100000000;
 527         case QIXIS_SYSCLK_125:
 528                 return 125000000;
 529         case QIXIS_SYSCLK_133:
 530                 return 133333333;
 531         }
 532         return 100000000;
 533 #else
 534         return 100000000;
 535 #endif
 536 }
 537
 538 unsigned long get_board_ddr_clk(void)
 539 {
 540 #ifdef CONFIG_TARGET_LX2160AQDS
 541         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 542
 543         switch ((ddrclk_conf & 0x30) >> 4) {
 544         case QIXIS_DDRCLK_100:
 545                 return 100000000;
 546         case QIXIS_DDRCLK_125:
 547                 return 125000000;
 548         case QIXIS_DDRCLK_133:
 549                 return 133333333;
 550         }
 551         return 100000000;
 552 #else
 553         return 100000000;
 554 #endif
 555 }
 556
 557 int board_init(void)
 558 {
 559 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 560         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 561 #endif
 562 #ifdef CONFIG_ENV_IS_NOWHERE
 563         gd->env_addr = (ulong)&default_environment[0];
 564 #endif
 565
 566         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 567
 568 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 569         /* invert AQR107 IRQ pins polarity */
 570         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 571 #endif
 572
 573 #ifdef CONFIG_FSL_CAAM
 574         sec_init();
 575 #endif
 576
 577         return 0;
 578 }
 579
 580 void detail_board_ddr_info(void)
 581 {
 582         int i;
 583         u64 ddr_size = 0;
 584
 585         puts("\nDDR    ");
 586         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 587                 ddr_size += gd->bd->bi_dram[i].size;
 588         print_size(ddr_size, "");
 589         print_ddr_info(0);
 590 }
 591
 592 #ifdef CONFIG_MISC_INIT_R
 593 int misc_init_r(void)
 594 {
 595         config_board_mux();
 596
 597         return 0;
 598 }
 599 #endif
 600
 601 #ifdef CONFIG_FSL_MC_ENET
 602 extern int fdt_fixup_board_phy(void *fdt);
 603
 604 void fdt_fixup_board_enet(void *fdt)
 605 {
 606         int offset;
 607
 608         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 609
 610         if (offset < 0)
 611                 offset = fdt_path_offset(fdt, "/fsl-mc");
 612
 613         if (offset < 0) {
 614                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 615                        __func__, offset);
 616                 return;
 617         }
 618
 619         if (get_mc_boot_status() == 0 &&
 620             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 621                 fdt_status_okay(fdt, offset);
 622                 fdt_fixup_board_phy(fdt);
 623         } else {
 624                 fdt_status_fail(fdt, offset);
 625         }
 626 }
 627
 628 void board_quiesce_devices(void)
 629 {
 630         fsl_mc_ldpaa_exit(gd->bd);
 631 }
 632 #endif
 633
 634 #ifdef CONFIG_OF_BOARD_SETUP
 635 int ft_board_setup(void *blob, bd_t *bd)
 636 {
 637         int i;
 638         u16 mc_memory_bank = 0;
 639
 640         u64 *base;
 641         u64 *size;
 642         u64 mc_memory_base = 0;
 643         u64 mc_memory_size = 0;
 644         u16 total_memory_banks;
 645         u64 gic_lpi_base;
 646
 647         ft_cpu_setup(blob, bd);
 648
 649         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 650
 651         if (mc_memory_base != 0)
 652                 mc_memory_bank++;
 653
 654         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 655
 656         base = calloc(total_memory_banks, sizeof(u64));
 657         size = calloc(total_memory_banks, sizeof(u64));
 658
 659         /* fixup DT for the three GPP DDR banks */
 660         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 661                 base[i] = gd->bd->bi_dram[i].start;
 662                 size[i] = gd->bd->bi_dram[i].size;
 663         }
 664
 665 #ifdef CONFIG_GIC_V3_ITS
 666         gic_lpi_base = gd->arch.resv_ram - GIC_LPI_SIZE;
 667         gic_lpi_tables_init(gic_lpi_base, cpu_numcores());
 668 #endif
 669
 670 #ifdef CONFIG_RESV_RAM
 671         /* reduce size if reserved memory is within this bank */
 672         if (gd->arch.resv_ram >= base[0] &&
 673             gd->arch.resv_ram < base[0] + size[0])
 674                 size[0] = gd->arch.resv_ram - base[0];
 675         else if (gd->arch.resv_ram >= base[1] &&
 676                  gd->arch.resv_ram < base[1] + size[1])
 677                 size[1] = gd->arch.resv_ram - base[1];
 678         else if (gd->arch.resv_ram >= base[2] &&
 679                  gd->arch.resv_ram < base[2] + size[2])
 680                 size[2] = gd->arch.resv_ram - base[2];
 681 #endif
 682
 683         if (mc_memory_base != 0) {
 684                 for (i = 0; i <= total_memory_banks; i++) {
 685                         if (base[i] == 0 && size[i] == 0) {
 686                                 base[i] = mc_memory_base;
 687                                 size[i] = mc_memory_size;
 688                                 break;
 689                         }
 690                 }
 691         }
 692
 693         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 694
 695 #ifdef CONFIG_USB
 696         fsl_fdt_fixup_dr_usb(blob, bd);
 697 #endif
 698
 699 #ifdef CONFIG_FSL_MC_ENET
 700         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 701         fdt_fixup_board_enet(blob);
 702 #endif
 703         fdt_fixup_icid(blob);
 704
 705         return 0;
 706 }
 707 #endif
 708
 709 void qixis_dump_switch(void)
 710 {
 711         int i, nr_of_cfgsw;
 712
 713         QIXIS_WRITE(cms[0], 0x00);
 714         nr_of_cfgsw = QIXIS_READ(cms[1]);
 715
 716         puts("DIP switch settings dump:\n");
 717         for (i = 1; i <= nr_of_cfgsw; i++) {
 718                 QIXIS_WRITE(cms[0], i);
 719                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 720         }
 721 }