board/freescale/lx2160a/lx2160a.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2018-2020 NXP
   4  */
   5
   6 #include <common.h>
   7 #include <clock_legacy.h>
   8 #include <dm.h>
   9 #include <dm/platform_data/serial_pl01x.h>
  10 #include <i2c.h>
  11 #include <malloc.h>
  12 #include <errno.h>
  13 #include <netdev.h>
  14 #include <fsl_ddr.h>
  15 #include <fsl_sec.h>
  16 #include <asm/io.h>
  17 #include <fdt_support.h>
  18 #include <linux/libfdt.h>
  19 #include <linux/sizes.h>
  20 #include <fsl-mc/fsl_mc.h>
  21 #include <env_internal.h>
  22 #include <efi_loader.h>
  23 #include <asm/arch/mmu.h>
  24 #include <hwconfig.h>
  25 #include <asm/arch/clock.h>
  26 #include <asm/arch/config.h>
  27 #include <asm/arch/fsl_serdes.h>
  28 #include <asm/arch/soc.h>
  29 #include "../common/qixis.h"
  30 #include "../common/vid.h"
  31 #include <fsl_immap.h>
  32 #include <asm/arch-fsl-layerscape/fsl_icid.h>
  33 #include <asm/gic-v3.h>
  34 #include <cpu_func.h>
  35
  36 #ifdef CONFIG_EMC2305
  37 #include "../common/emc2305.h"
  38 #endif
  39
  40 #define GIC_LPI_SIZE                             0x200000
  41 #ifdef CONFIG_TARGET_LX2160AQDS
  42 #define CFG_MUX_I2C_SDHC(reg, value)            ((reg & 0x3f) | value)
  43 #define SET_CFG_MUX1_SDHC1_SDHC(reg)            (reg & 0x3f)
  44 #define SET_CFG_MUX2_SDHC1_SPI(reg, value)      ((reg & 0xcf) | value)
  45 #define SET_CFG_MUX3_SDHC1_SPI(reg, value)      ((reg & 0xf8) | value)
  46 #define SET_CFG_MUX_SDHC2_DSPI(reg, value)      ((reg & 0xf8) | value)
  47 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value)     ((reg & 0x3f) | value)
  48 #define SDHC1_BASE_PMUX_DSPI                    2
  49 #define SDHC2_BASE_PMUX_DSPI                    2
  50 #define IIC5_PMUX_SPI3                          3
  51 #endif /* CONFIG_TARGET_LX2160AQDS */
  52
  53 DECLARE_GLOBAL_DATA_PTR;
  54
  55 static struct pl01x_serial_platdata serial0 = {
  56 #if CONFIG_CONS_INDEX == 0
  57         .base = CONFIG_SYS_SERIAL0,
  58 #elif CONFIG_CONS_INDEX == 1
  59         .base = CONFIG_SYS_SERIAL1,
  60 #else
  61 #error "Unsupported console index value."
  62 #endif
  63         .type = TYPE_PL011,
  64 };
  65
  66 U_BOOT_DEVICE(nxp_serial0) = {
  67         .name = "serial_pl01x",
  68         .platdata = &serial0,
  69 };
  70
  71 static struct pl01x_serial_platdata serial1 = {
  72         .base = CONFIG_SYS_SERIAL1,
  73         .type = TYPE_PL011,
  74 };
  75
  76 U_BOOT_DEVICE(nxp_serial1) = {
  77         .name = "serial_pl01x",
  78         .platdata = &serial1,
  79 };
  80
  81 int select_i2c_ch_pca9547(u8 ch)
  82 {
  83         int ret;
  84
  85 #ifndef CONFIG_DM_I2C
  86         ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
  87 #else
  88         struct udevice *dev;
  89
  90         ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
  91         if (!ret)
  92                 ret = dm_i2c_write(dev, 0, &ch, 1);
  93 #endif
  94         if (ret) {
  95                 puts("PCA: failed to select proper channel\n");
  96                 return ret;
  97         }
  98
  99         return 0;
 100 }
 101
 102 static void uart_get_clock(void)
 103 {
 104         serial0.clock = get_serial_clock();
 105         serial1.clock = get_serial_clock();
 106 }
 107
 108 int board_early_init_f(void)
 109 {
 110 #ifdef CONFIG_SYS_I2C_EARLY_INIT
 111         i2c_early_init_f();
 112 #endif
 113         /* get required clock for UART IP */
 114         uart_get_clock();
 115
 116 #ifdef CONFIG_EMC2305
 117         select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
 118         emc2305_init();
 119         set_fan_speed(I2C_EMC2305_PWM);
 120         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 121 #endif
 122
 123         fsl_lsch3_early_init_f();
 124         return 0;
 125 }
 126
 127 #ifdef CONFIG_OF_BOARD_FIXUP
 128 int board_fix_fdt(void *fdt)
 129 {
 130         char *reg_names, *reg_name;
 131         int names_len, old_name_len, new_name_len, remaining_names_len;
 132         struct str_map {
 133                 char *old_str;
 134                 char *new_str;
 135         } reg_names_map[] = {
 136                 { "ccsr", "dbi" },
 137                 { "pf_ctrl", "ctrl" }
 138         };
 139         int off = -1, i = 0;
 140
 141         if (IS_SVR_REV(get_svr(), 1, 0))
 142                 return 0;
 143
 144         off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
 145         while (off != -FDT_ERR_NOTFOUND) {
 146                 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
 147                             strlen("fsl,ls-pcie") + 1);
 148
 149                 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
 150                                                 &names_len);
 151                 if (!reg_names)
 152                         continue;
 153
 154                 reg_name = reg_names;
 155                 remaining_names_len = names_len - (reg_name - reg_names);
 156                 i = 0;
 157                 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
 158                         old_name_len = strlen(reg_names_map[i].old_str);
 159                         new_name_len = strlen(reg_names_map[i].new_str);
 160                         if (memcmp(reg_name, reg_names_map[i].old_str,
 161                                    old_name_len) == 0) {
 162                                 /* first only leave required bytes for new_str
 163                                  * and copy rest of the string after it
 164                                  */
 165                                 memcpy(reg_name + new_name_len,
 166                                        reg_name + old_name_len,
 167                                        remaining_names_len - old_name_len);
 168                                 /* Now copy new_str */
 169                                 memcpy(reg_name, reg_names_map[i].new_str,
 170                                        new_name_len);
 171                                 names_len -= old_name_len;
 172                                 names_len += new_name_len;
 173                                 i++;
 174                         }
 175
 176                         reg_name = memchr(reg_name, '\0', remaining_names_len);
 177                         if (!reg_name)
 178                                 break;
 179
 180                         reg_name += 1;
 181
 182                         remaining_names_len = names_len -
 183                                               (reg_name - reg_names);
 184                 }
 185
 186                 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
 187                 off = fdt_node_offset_by_compatible(fdt, off,
 188                                                     "fsl,lx2160a-pcie");
 189         }
 190
 191         return 0;
 192 }
 193 #endif
 194
 195 #if defined(CONFIG_TARGET_LX2160AQDS)
 196 void esdhc_dspi_status_fixup(void *blob)
 197 {
 198         const char esdhc0_path[] = "/soc/esdhc@2140000";
 199         const char esdhc1_path[] = "/soc/esdhc@2150000";
 200         const char dspi0_path[] = "/soc/spi@2100000";
 201         const char dspi1_path[] = "/soc/spi@2110000";
 202         const char dspi2_path[] = "/soc/spi@2120000";
 203
 204         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 205         u32 sdhc1_base_pmux;
 206         u32 sdhc2_base_pmux;
 207         u32 iic5_pmux;
 208
 209         /* Check RCW field sdhc1_base_pmux to enable/disable
 210          * esdhc0/dspi0 DT node
 211          */
 212         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 213                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 214         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 215
 216         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 217                 do_fixup_by_path(blob, dspi0_path, "status", "okay",
 218                                  sizeof("okay"), 1);
 219                 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
 220                                  sizeof("disabled"), 1);
 221         } else {
 222                 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
 223                                  sizeof("okay"), 1);
 224                 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
 225                                  sizeof("disabled"), 1);
 226         }
 227
 228         /* Check RCW field sdhc2_base_pmux to enable/disable
 229          * esdhc1/dspi1 DT node
 230          */
 231         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 232                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 233         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 234
 235         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 236                 do_fixup_by_path(blob, dspi1_path, "status", "okay",
 237                                  sizeof("okay"), 1);
 238                 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
 239                                  sizeof("disabled"), 1);
 240         } else {
 241                 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
 242                                  sizeof("okay"), 1);
 243                 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
 244                                  sizeof("disabled"), 1);
 245         }
 246
 247         /* Check RCW field IIC5 to enable dspi2 DT node */
 248         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 249                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 250         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 251
 252         if (iic5_pmux == IIC5_PMUX_SPI3)
 253                 do_fixup_by_path(blob, dspi2_path, "status", "okay",
 254                                  sizeof("okay"), 1);
 255         else
 256                 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
 257                                  sizeof("disabled"), 1);
 258 }
 259 #endif
 260
 261 int esdhc_status_fixup(void *blob, const char *compat)
 262 {
 263 #if defined(CONFIG_TARGET_LX2160AQDS)
 264         /* Enable esdhc and dspi DT nodes based on RCW fields */
 265         esdhc_dspi_status_fixup(blob);
 266 #else
 267         /* Enable both esdhc DT nodes for LX2160ARDB */
 268         do_fixup_by_compat(blob, compat, "status", "okay",
 269                            sizeof("okay"), 1);
 270 #endif
 271         return 0;
 272 }
 273
 274 #if defined(CONFIG_VID)
 275 int i2c_multiplexer_select_vid_channel(u8 channel)
 276 {
 277         return select_i2c_ch_pca9547(channel);
 278 }
 279
 280 int init_func_vid(void)
 281 {
 282         int set_vid;
 283
 284         if (IS_SVR_REV(get_svr(), 1, 0))
 285                 set_vid = adjust_vdd(800);
 286         else
 287                 set_vid = adjust_vdd(0);
 288
 289         if (set_vid < 0)
 290                 printf("core voltage not adjusted\n");
 291
 292         return 0;
 293 }
 294 #endif
 295
 296 int checkboard(void)
 297 {
 298         enum boot_src src = get_boot_src();
 299         char buf[64];
 300         u8 sw;
 301 #ifdef CONFIG_TARGET_LX2160AQDS
 302         int clock;
 303         static const char *const freq[] = {"100", "125", "156.25",
 304                                            "161.13", "322.26", "", "", "",
 305                                            "", "", "", "", "", "", "",
 306                                            "100 separate SSCG"};
 307 #endif
 308
 309         cpu_name(buf);
 310 #ifdef CONFIG_TARGET_LX2160AQDS
 311         printf("Board: %s-QDS, ", buf);
 312 #else
 313         printf("Board: %s-RDB, ", buf);
 314 #endif
 315
 316         sw = QIXIS_READ(arch);
 317         printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
 318
 319         if (src == BOOT_SOURCE_SD_MMC) {
 320                 puts("SD\n");
 321         } else if (src == BOOT_SOURCE_SD_MMC2) {
 322                 puts("eMMC\n");
 323         } else {
 324                 sw = QIXIS_READ(brdcfg[0]);
 325                 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
 326                 switch (sw) {
 327                 case 0:
 328                 case 4:
 329                         puts("FlexSPI DEV#0\n");
 330                         break;
 331                 case 1:
 332                         puts("FlexSPI DEV#1\n");
 333                         break;
 334                 case 2:
 335                 case 3:
 336                         puts("FlexSPI EMU\n");
 337                         break;
 338                 default:
 339                         printf("invalid setting, xmap: %d\n", sw);
 340                         break;
 341                 }
 342         }
 343 #ifdef CONFIG_TARGET_LX2160AQDS
 344         printf("FPGA: v%d (%s), build %d",
 345                (int)QIXIS_READ(scver), qixis_read_tag(buf),
 346                (int)qixis_read_minor());
 347         /* the timestamp string contains "\n" at the end */
 348         printf(" on %s", qixis_read_time(buf));
 349
 350         puts("SERDES1 Reference : ");
 351         sw = QIXIS_READ(brdcfg[2]);
 352         clock = sw >> 4;
 353         printf("Clock1 = %sMHz ", freq[clock]);
 354         clock = sw & 0x0f;
 355         printf("Clock2 = %sMHz", freq[clock]);
 356
 357         sw = QIXIS_READ(brdcfg[3]);
 358         puts("\nSERDES2 Reference : ");
 359         clock = sw >> 4;
 360         printf("Clock1 = %sMHz ", freq[clock]);
 361         clock = sw & 0x0f;
 362         printf("Clock2 = %sMHz", freq[clock]);
 363
 364         sw = QIXIS_READ(brdcfg[12]);
 365         puts("\nSERDES3 Reference : ");
 366         clock = sw >> 4;
 367         printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
 368 #else
 369         printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
 370
 371         puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
 372         puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 373         puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
 374 #endif
 375         return 0;
 376 }
 377
 378 #ifdef CONFIG_TARGET_LX2160AQDS
 379 /*
 380  * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
 381  */
 382 u8 qixis_esdhc_detect_quirk(void)
 383 {
 384         /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
 385          * SDHC1 Card ID:
 386          * Specifies the type of card installed in the SDHC1 adapter slot.
 387          * 000= (reserved)
 388          * 001= eMMC V4.5 adapter is installed.
 389          * 010= SD/MMC 3.3V adapter is installed.
 390          * 011= eMMC V4.4 adapter is installed.
 391          * 100= eMMC V5.0 adapter is installed.
 392          * 101= MMC card/Legacy (3.3V) adapter is installed.
 393          * 110= SDCard V2/V3 adapter installed.
 394          * 111= no adapter is installed.
 395          */
 396         return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
 397                  QIXIS_ESDHC_NO_ADAPTER);
 398 }
 399
 400 int config_board_mux(void)
 401 {
 402         u8 reg11, reg5, reg13;
 403         struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
 404         u32 sdhc1_base_pmux;
 405         u32 sdhc2_base_pmux;
 406         u32 iic5_pmux;
 407
 408         /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
 409          * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
 410          * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
 411          * Qixis and remote systems are isolated from the I2C1 bus.
 412          * Processor connections are still available.
 413          * SPI2 CS2_B controls EN25S64 SPI memory device.
 414          * SPI3 CS2_B controls EN25S64 SPI memory device.
 415          * EC2 connects to PHY #2 using RGMII protocol.
 416          * CLK_OUT connects to FPGA for clock measurement.
 417          */
 418
 419         reg5 = QIXIS_READ(brdcfg[5]);
 420         reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
 421         QIXIS_WRITE(brdcfg[5], reg5);
 422
 423         /* Check RCW field sdhc1_base_pmux
 424          * esdhc0 : sdhc1_base_pmux = 0
 425          * dspi0  : sdhc1_base_pmux = 2
 426          */
 427         sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 428                 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
 429         sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
 430
 431         if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
 432                 reg11 = QIXIS_READ(brdcfg[11]);
 433                 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
 434                 QIXIS_WRITE(brdcfg[11], reg11);
 435         } else {
 436                 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
 437                  *          {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
 438                  *          {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
 439                  */
 440                 reg11 = QIXIS_READ(brdcfg[11]);
 441                 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
 442                 QIXIS_WRITE(brdcfg[11], reg11);
 443         }
 444
 445         /* Check RCW field sdhc2_base_pmux
 446          * esdhc1 : sdhc2_base_pmux = 0 (default)
 447          * dspi1  : sdhc2_base_pmux = 2
 448          */
 449         sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
 450                 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
 451         sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
 452
 453         if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
 454                 reg13 = QIXIS_READ(brdcfg[13]);
 455                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
 456                 QIXIS_WRITE(brdcfg[13], reg13);
 457         } else {
 458                 reg13 = QIXIS_READ(brdcfg[13]);
 459                 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
 460                 QIXIS_WRITE(brdcfg[13], reg13);
 461         }
 462
 463         /* Check RCW field IIC5 to enable dspi2 DT nodei
 464          * dspi2: IIC5 = 3
 465          */
 466         iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
 467                 & FSL_CHASSIS3_IIC5_PMUX_MASK;
 468         iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
 469
 470         if (iic5_pmux == IIC5_PMUX_SPI3) {
 471                 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
 472                 reg11 = QIXIS_READ(brdcfg[11]);
 473                 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
 474                 QIXIS_WRITE(brdcfg[11], reg11);
 475
 476                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
 477                  * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
 478                  * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
 479                  */
 480                 reg11 = QIXIS_READ(brdcfg[11]);
 481                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
 482                 QIXIS_WRITE(brdcfg[11], reg11);
 483         } else {
 484                 /*
 485                  * If {SDHC1_DAT4} has been configured to route to SDHC1_VS,
 486                  * do not change it.
 487                  * Otherwise route {SDHC1_DAT4} to SDHC1 adapter slot.
 488                  */
 489                 reg11 = QIXIS_READ(brdcfg[11]);
 490                 if ((reg11 & 0x30) != 0x30) {
 491                         reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
 492                         QIXIS_WRITE(brdcfg[11], reg11);
 493                 }
 494
 495                 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
 496                  * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
 497                  * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
 498                  */
 499                 reg11 = QIXIS_READ(brdcfg[11]);
 500                 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
 501                 QIXIS_WRITE(brdcfg[11], reg11);
 502         }
 503
 504         return 0;
 505 }
 506 #elif defined(CONFIG_TARGET_LX2160ARDB)
 507 int config_board_mux(void)
 508 {
 509         u8 brdcfg;
 510
 511         brdcfg = QIXIS_READ(brdcfg[4]);
 512         /* The BRDCFG4 register controls general board configuration.
 513          *|-------------------------------------------|
 514          *|Field  | Function                          |
 515          *|-------------------------------------------|
 516          *|5      | CAN I/O Enable (net CFG_CAN_EN_B):|
 517          *|CAN_EN | 0= CAN transceivers are disabled. |
 518          *|       | 1= CAN transceivers are enabled.  |
 519          *|-------------------------------------------|
 520          */
 521         brdcfg |= BIT_MASK(5);
 522         QIXIS_WRITE(brdcfg[4], brdcfg);
 523
 524         return 0;
 525 }
 526 #else
 527 int config_board_mux(void)
 528 {
 529         return 0;
 530 }
 531 #endif
 532
 533 unsigned long get_board_sys_clk(void)
 534 {
 535 #ifdef CONFIG_TARGET_LX2160AQDS
 536         u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
 537
 538         switch (sysclk_conf & 0x03) {
 539         case QIXIS_SYSCLK_100:
 540                 return 100000000;
 541         case QIXIS_SYSCLK_125:
 542                 return 125000000;
 543         case QIXIS_SYSCLK_133:
 544                 return 133333333;
 545         }
 546         return 100000000;
 547 #else
 548         return 100000000;
 549 #endif
 550 }
 551
 552 unsigned long get_board_ddr_clk(void)
 553 {
 554 #ifdef CONFIG_TARGET_LX2160AQDS
 555         u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
 556
 557         switch ((ddrclk_conf & 0x30) >> 4) {
 558         case QIXIS_DDRCLK_100:
 559                 return 100000000;
 560         case QIXIS_DDRCLK_125:
 561                 return 125000000;
 562         case QIXIS_DDRCLK_133:
 563                 return 133333333;
 564         }
 565         return 100000000;
 566 #else
 567         return 100000000;
 568 #endif
 569 }
 570
 571 int board_init(void)
 572 {
 573 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 574         u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
 575 #endif
 576 #ifdef CONFIG_ENV_IS_NOWHERE
 577         gd->env_addr = (ulong)&default_environment[0];
 578 #endif
 579
 580         select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
 581
 582 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
 583         /* invert AQR107 IRQ pins polarity */
 584         out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
 585 #endif
 586
 587 #ifdef CONFIG_FSL_CAAM
 588         sec_init();
 589 #endif
 590
 591         return 0;
 592 }
 593
 594 void detail_board_ddr_info(void)
 595 {
 596         int i;
 597         u64 ddr_size = 0;
 598
 599         puts("\nDDR    ");
 600         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
 601                 ddr_size += gd->bd->bi_dram[i].size;
 602         print_size(ddr_size, "");
 603         print_ddr_info(0);
 604 }
 605
 606 #ifdef CONFIG_MISC_INIT_R
 607 int misc_init_r(void)
 608 {
 609         config_board_mux();
 610
 611         return 0;
 612 }
 613 #endif
 614
 615 #ifdef CONFIG_FSL_MC_ENET
 616 extern int fdt_fixup_board_phy(void *fdt);
 617
 618 void fdt_fixup_board_enet(void *fdt)
 619 {
 620         int offset;
 621
 622         offset = fdt_path_offset(fdt, "/soc/fsl-mc");
 623
 624         if (offset < 0)
 625                 offset = fdt_path_offset(fdt, "/fsl-mc");
 626
 627         if (offset < 0) {
 628                 printf("%s: fsl-mc node not found in device tree (error %d)\n",
 629                        __func__, offset);
 630                 return;
 631         }
 632
 633         if (get_mc_boot_status() == 0 &&
 634             (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
 635                 fdt_status_okay(fdt, offset);
 636                 fdt_fixup_board_phy(fdt);
 637         } else {
 638                 fdt_status_fail(fdt, offset);
 639         }
 640 }
 641
 642 void board_quiesce_devices(void)
 643 {
 644         fsl_mc_ldpaa_exit(gd->bd);
 645 }
 646 #endif
 647
 648 #ifdef CONFIG_GIC_V3_ITS
 649 int fdt_fixup_gic_lpi_memory(void *blob, u64 gic_lpi_base)
 650 {
 651         u32 phandle;
 652         int err;
 653         struct fdt_memory gic_lpi;
 654
 655         gic_lpi.start = gic_lpi_base;
 656         gic_lpi.end = gic_lpi_base + GIC_LPI_SIZE - 1;
 657         err = fdtdec_add_reserved_memory(blob, "gic-lpi", &gic_lpi, &phandle);
 658         if (err < 0)
 659                 debug("failed to add reserved memory: %d\n", err);
 660
 661         return err;
 662 }
 663 #endif
 664
 665 #ifdef CONFIG_OF_BOARD_SETUP
 666 int ft_board_setup(void *blob, bd_t *bd)
 667 {
 668         int i;
 669         u16 mc_memory_bank = 0;
 670
 671         u64 *base;
 672         u64 *size;
 673         u64 mc_memory_base = 0;
 674         u64 mc_memory_size = 0;
 675         u16 total_memory_banks;
 676         u64 __maybe_unused gic_lpi_base;
 677         int ret;
 678
 679         ft_cpu_setup(blob, bd);
 680
 681         fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
 682
 683         if (mc_memory_base != 0)
 684                 mc_memory_bank++;
 685
 686         total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
 687
 688         base = calloc(total_memory_banks, sizeof(u64));
 689         size = calloc(total_memory_banks, sizeof(u64));
 690
 691         /* fixup DT for the three GPP DDR banks */
 692         for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
 693                 base[i] = gd->bd->bi_dram[i].start;
 694                 size[i] = gd->bd->bi_dram[i].size;
 695         }
 696
 697 #ifdef CONFIG_GIC_V3_ITS
 698         gic_lpi_base = ALIGN(gd->arch.resv_ram - GIC_LPI_SIZE, SZ_64K);
 699         ret = fdt_fixup_gic_lpi_memory(blob, gic_lpi_base);
 700         if (!ret && gic_lpi_tables_init(gic_lpi_base, cpu_numcores()))
 701                 debug("%s: failed to init gic-lpi-tables\n", __func__);
 702 #endif
 703
 704 #ifdef CONFIG_RESV_RAM
 705         /* reduce size if reserved memory is within this bank */
 706         if (gd->arch.resv_ram >= base[0] &&
 707             gd->arch.resv_ram < base[0] + size[0])
 708                 size[0] = gd->arch.resv_ram - base[0];
 709         else if (gd->arch.resv_ram >= base[1] &&
 710                  gd->arch.resv_ram < base[1] + size[1])
 711                 size[1] = gd->arch.resv_ram - base[1];
 712         else if (gd->arch.resv_ram >= base[2] &&
 713                  gd->arch.resv_ram < base[2] + size[2])
 714                 size[2] = gd->arch.resv_ram - base[2];
 715 #endif
 716
 717         if (mc_memory_base != 0) {
 718                 for (i = 0; i <= total_memory_banks; i++) {
 719                         if (base[i] == 0 && size[i] == 0) {
 720                                 base[i] = mc_memory_base;
 721                                 size[i] = mc_memory_size;
 722                                 break;
 723                         }
 724                 }
 725         }
 726
 727         fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
 728
 729 #ifdef CONFIG_USB
 730         fsl_fdt_fixup_dr_usb(blob, bd);
 731 #endif
 732
 733 #ifdef CONFIG_FSL_MC_ENET
 734         fdt_fsl_mc_fixup_iommu_map_entry(blob);
 735         fdt_fixup_board_enet(blob);
 736 #endif
 737         fdt_fixup_icid(blob);
 738
 739         return 0;
 740 }
 741 #endif
 742
 743 void qixis_dump_switch(void)
 744 {
 745         int i, nr_of_cfgsw;
 746
 747         QIXIS_WRITE(cms[0], 0x00);
 748         nr_of_cfgsw = QIXIS_READ(cms[1]);
 749
 750         puts("DIP switch settings dump:\n");
 751         for (i = 1; i <= nr_of_cfgsw; i++) {
 752                 QIXIS_WRITE(cms[0], i);
 753                 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));
 754         }
 755 }