1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <clock_legacy.h>
9 #include <dm/platform_data/serial_pl01x.h>
17 #include <fdt_support.h>
18 #include <linux/libfdt.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <env_internal.h>
21 #include <efi_loader.h>
22 #include <asm/arch/mmu.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/config.h>
26 #include <asm/arch/fsl_serdes.h>
27 #include <asm/arch/soc.h>
28 #include "../common/qixis.h"
29 #include "../common/vid.h"
30 #include <fsl_immap.h>
31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
34 #include "../common/emc2305.h"
37 #ifdef CONFIG_TARGET_LX2160AQDS
38 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
39 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
40 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
41 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
42 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
43 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
44 #define SDHC1_BASE_PMUX_DSPI 2
45 #define SDHC2_BASE_PMUX_DSPI 2
46 #define IIC5_PMUX_SPI3 3
47 #endif /* CONFIG_TARGET_LX2160AQDS */
49 DECLARE_GLOBAL_DATA_PTR;
51 static struct pl01x_serial_platdata serial0 = {
52 #if CONFIG_CONS_INDEX == 0
53 .base = CONFIG_SYS_SERIAL0,
54 #elif CONFIG_CONS_INDEX == 1
55 .base = CONFIG_SYS_SERIAL1,
57 #error "Unsupported console index value."
62 U_BOOT_DEVICE(nxp_serial0) = {
63 .name = "serial_pl01x",
67 static struct pl01x_serial_platdata serial1 = {
68 .base = CONFIG_SYS_SERIAL1,
72 U_BOOT_DEVICE(nxp_serial1) = {
73 .name = "serial_pl01x",
77 int select_i2c_ch_pca9547(u8 ch)
82 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
88 ret = dm_i2c_write(dev, 0, &ch, 1);
91 puts("PCA: failed to select proper channel\n");
98 static void uart_get_clock(void)
100 serial0.clock = get_serial_clock();
101 serial1.clock = get_serial_clock();
104 int board_early_init_f(void)
106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
109 /* get required clock for UART IP */
112 #ifdef CONFIG_EMC2305
113 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
115 set_fan_speed(I2C_EMC2305_PWM);
116 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
119 fsl_lsch3_early_init_f();
123 #ifdef CONFIG_OF_BOARD_FIXUP
124 int board_fix_fdt(void *fdt)
126 char *reg_names, *reg_name;
127 int names_len, old_name_len, new_name_len, remaining_names_len;
131 } reg_names_map[] = {
133 { "pf_ctrl", "ctrl" }
137 if (IS_SVR_REV(get_svr(), 1, 0))
140 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
141 while (off != -FDT_ERR_NOTFOUND) {
142 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
143 strlen("fsl,ls-pcie") + 1);
145 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
150 reg_name = reg_names;
151 remaining_names_len = names_len - (reg_name - reg_names);
152 for (i = 0; (i < ARRAY_SIZE(reg_names_map)) && names_len; i++) {
153 old_name_len = strlen(reg_names_map[i].old_str);
154 new_name_len = strlen(reg_names_map[i].new_str);
155 if (memcmp(reg_name, reg_names_map[i].old_str,
156 old_name_len) == 0) {
157 /* first only leave required bytes for new_str
158 * and copy rest of the string after it
160 memcpy(reg_name + new_name_len,
161 reg_name + old_name_len,
162 remaining_names_len - old_name_len);
163 /* Now copy new_str */
164 memcpy(reg_name, reg_names_map[i].new_str,
166 names_len -= old_name_len;
167 names_len += new_name_len;
170 reg_name = memchr(reg_name, '\0', remaining_names_len);
176 remaining_names_len = names_len -
177 (reg_name - reg_names);
180 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
181 off = fdt_node_offset_by_compatible(fdt, off,
189 #if defined(CONFIG_TARGET_LX2160AQDS)
190 void esdhc_dspi_status_fixup(void *blob)
192 const char esdhc0_path[] = "/soc/esdhc@2140000";
193 const char esdhc1_path[] = "/soc/esdhc@2150000";
194 const char dspi0_path[] = "/soc/spi@2100000";
195 const char dspi1_path[] = "/soc/spi@2110000";
196 const char dspi2_path[] = "/soc/spi@2120000";
198 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
203 /* Check RCW field sdhc1_base_pmux to enable/disable
204 * esdhc0/dspi0 DT node
206 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
207 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
208 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
210 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
211 do_fixup_by_path(blob, dspi0_path, "status", "okay",
213 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
214 sizeof("disabled"), 1);
216 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
218 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
219 sizeof("disabled"), 1);
222 /* Check RCW field sdhc2_base_pmux to enable/disable
223 * esdhc1/dspi1 DT node
225 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
226 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
227 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
229 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
230 do_fixup_by_path(blob, dspi1_path, "status", "okay",
232 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
233 sizeof("disabled"), 1);
235 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
237 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
238 sizeof("disabled"), 1);
241 /* Check RCW field IIC5 to enable dspi2 DT node */
242 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
243 & FSL_CHASSIS3_IIC5_PMUX_MASK;
244 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
246 if (iic5_pmux == IIC5_PMUX_SPI3)
247 do_fixup_by_path(blob, dspi2_path, "status", "okay",
250 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
251 sizeof("disabled"), 1);
255 int esdhc_status_fixup(void *blob, const char *compat)
257 #if defined(CONFIG_TARGET_LX2160AQDS)
258 /* Enable esdhc and dspi DT nodes based on RCW fields */
259 esdhc_dspi_status_fixup(blob);
261 /* Enable both esdhc DT nodes for LX2160ARDB */
262 do_fixup_by_compat(blob, compat, "status", "okay",
268 #if defined(CONFIG_VID)
269 int i2c_multiplexer_select_vid_channel(u8 channel)
271 return select_i2c_ch_pca9547(channel);
274 int init_func_vid(void)
276 if (adjust_vdd(0) < 0)
277 printf("core voltage not adjusted\n");
285 enum boot_src src = get_boot_src();
288 #ifdef CONFIG_TARGET_LX2160AQDS
290 static const char *const freq[] = {"100", "125", "156.25",
291 "161.13", "322.26", "", "", "",
292 "", "", "", "", "", "", "",
293 "100 separate SSCG"};
297 #ifdef CONFIG_TARGET_LX2160AQDS
298 printf("Board: %s-QDS, ", buf);
300 printf("Board: %s-RDB, ", buf);
303 sw = QIXIS_READ(arch);
304 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
306 if (src == BOOT_SOURCE_SD_MMC) {
309 sw = QIXIS_READ(brdcfg[0]);
310 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
314 puts("FlexSPI DEV#0\n");
317 puts("FlexSPI DEV#1\n");
321 puts("FlexSPI EMU\n");
324 printf("invalid setting, xmap: %d\n", sw);
328 #ifdef CONFIG_TARGET_LX2160AQDS
329 printf("FPGA: v%d (%s), build %d",
330 (int)QIXIS_READ(scver), qixis_read_tag(buf),
331 (int)qixis_read_minor());
332 /* the timestamp string contains "\n" at the end */
333 printf(" on %s", qixis_read_time(buf));
335 puts("SERDES1 Reference : ");
336 sw = QIXIS_READ(brdcfg[2]);
338 printf("Clock1 = %sMHz ", freq[clock]);
340 printf("Clock2 = %sMHz", freq[clock]);
342 sw = QIXIS_READ(brdcfg[3]);
343 puts("\nSERDES2 Reference : ");
345 printf("Clock1 = %sMHz ", freq[clock]);
347 printf("Clock2 = %sMHz", freq[clock]);
349 sw = QIXIS_READ(brdcfg[12]);
350 puts("\nSERDES3 Reference : ");
352 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
354 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
356 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
357 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
358 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
363 #ifdef CONFIG_TARGET_LX2160AQDS
365 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
367 u8 qixis_esdhc_detect_quirk(void)
369 /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
371 * Specifies the type of card installed in the SDHC1 adapter slot.
373 * 001= eMMC V4.5 adapter is installed.
374 * 010= SD/MMC 3.3V adapter is installed.
375 * 011= eMMC V4.4 adapter is installed.
376 * 100= eMMC V5.0 adapter is installed.
377 * 101= MMC card/Legacy (3.3V) adapter is installed.
378 * 110= SDCard V2/V3 adapter installed.
379 * 111= no adapter is installed.
381 return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
382 QIXIS_ESDHC_NO_ADAPTER);
385 int config_board_mux(void)
387 u8 reg11, reg5, reg13;
388 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
393 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
394 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
395 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
396 * Qixis and remote systems are isolated from the I2C1 bus.
397 * Processor connections are still available.
398 * SPI2 CS2_B controls EN25S64 SPI memory device.
399 * SPI3 CS2_B controls EN25S64 SPI memory device.
400 * EC2 connects to PHY #2 using RGMII protocol.
401 * CLK_OUT connects to FPGA for clock measurement.
404 reg5 = QIXIS_READ(brdcfg[5]);
405 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
406 QIXIS_WRITE(brdcfg[5], reg5);
408 /* Check RCW field sdhc1_base_pmux
409 * esdhc0 : sdhc1_base_pmux = 0
410 * dspi0 : sdhc1_base_pmux = 2
412 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
413 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
414 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
416 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
417 reg11 = QIXIS_READ(brdcfg[11]);
418 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
419 QIXIS_WRITE(brdcfg[11], reg11);
421 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
422 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
423 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
425 reg11 = QIXIS_READ(brdcfg[11]);
426 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
427 QIXIS_WRITE(brdcfg[11], reg11);
430 /* Check RCW field sdhc2_base_pmux
431 * esdhc1 : sdhc2_base_pmux = 0 (default)
432 * dspi1 : sdhc2_base_pmux = 2
434 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
435 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
436 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
438 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
439 reg13 = QIXIS_READ(brdcfg[13]);
440 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
441 QIXIS_WRITE(brdcfg[13], reg13);
443 reg13 = QIXIS_READ(brdcfg[13]);
444 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
445 QIXIS_WRITE(brdcfg[13], reg13);
448 /* Check RCW field IIC5 to enable dspi2 DT nodei
451 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
452 & FSL_CHASSIS3_IIC5_PMUX_MASK;
453 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
455 if (iic5_pmux == IIC5_PMUX_SPI3) {
456 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
457 reg11 = QIXIS_READ(brdcfg[11]);
458 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
459 QIXIS_WRITE(brdcfg[11], reg11);
461 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
462 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
463 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
465 reg11 = QIXIS_READ(brdcfg[11]);
466 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
467 QIXIS_WRITE(brdcfg[11], reg11);
469 /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
470 reg11 = QIXIS_READ(brdcfg[11]);
471 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
472 QIXIS_WRITE(brdcfg[11], reg11);
474 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
475 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
476 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
478 reg11 = QIXIS_READ(brdcfg[11]);
479 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
480 QIXIS_WRITE(brdcfg[11], reg11);
485 #elif defined(CONFIG_TARGET_LX2160ARDB)
486 int config_board_mux(void)
490 brdcfg = QIXIS_READ(brdcfg[4]);
491 /* The BRDCFG4 register controls general board configuration.
492 *|-------------------------------------------|
494 *|-------------------------------------------|
495 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
496 *|CAN_EN | 0= CAN transceivers are disabled. |
497 *| | 1= CAN transceivers are enabled. |
498 *|-------------------------------------------|
500 brdcfg |= BIT_MASK(5);
501 QIXIS_WRITE(brdcfg[4], brdcfg);
506 int config_board_mux(void)
512 unsigned long get_board_sys_clk(void)
514 #ifdef CONFIG_TARGET_LX2160AQDS
515 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
517 switch (sysclk_conf & 0x03) {
518 case QIXIS_SYSCLK_100:
520 case QIXIS_SYSCLK_125:
522 case QIXIS_SYSCLK_133:
531 unsigned long get_board_ddr_clk(void)
533 #ifdef CONFIG_TARGET_LX2160AQDS
534 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
536 switch ((ddrclk_conf & 0x30) >> 4) {
537 case QIXIS_DDRCLK_100:
539 case QIXIS_DDRCLK_125:
541 case QIXIS_DDRCLK_133:
552 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
553 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
555 #ifdef CONFIG_ENV_IS_NOWHERE
556 gd->env_addr = (ulong)&default_environment[0];
559 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
561 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
562 /* invert AQR107 IRQ pins polarity */
563 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
566 #ifdef CONFIG_FSL_CAAM
573 void detail_board_ddr_info(void)
579 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
580 ddr_size += gd->bd->bi_dram[i].size;
581 print_size(ddr_size, "");
585 #if defined(CONFIG_ARCH_MISC_INIT)
586 int arch_misc_init(void)
594 #ifdef CONFIG_FSL_MC_ENET
595 extern int fdt_fixup_board_phy(void *fdt);
597 void fdt_fixup_board_enet(void *fdt)
601 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
604 offset = fdt_path_offset(fdt, "/fsl-mc");
607 printf("%s: fsl-mc node not found in device tree (error %d)\n",
612 if (get_mc_boot_status() == 0 &&
613 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
614 fdt_status_okay(fdt, offset);
615 fdt_fixup_board_phy(fdt);
617 fdt_status_fail(fdt, offset);
621 void board_quiesce_devices(void)
623 fsl_mc_ldpaa_exit(gd->bd);
627 #ifdef CONFIG_OF_BOARD_SETUP
629 int ft_board_setup(void *blob, bd_t *bd)
632 u16 mc_memory_bank = 0;
636 u64 mc_memory_base = 0;
637 u64 mc_memory_size = 0;
638 u16 total_memory_banks;
640 ft_cpu_setup(blob, bd);
642 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
644 if (mc_memory_base != 0)
647 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
649 base = calloc(total_memory_banks, sizeof(u64));
650 size = calloc(total_memory_banks, sizeof(u64));
652 /* fixup DT for the three GPP DDR banks */
653 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
654 base[i] = gd->bd->bi_dram[i].start;
655 size[i] = gd->bd->bi_dram[i].size;
658 #ifdef CONFIG_RESV_RAM
659 /* reduce size if reserved memory is within this bank */
660 if (gd->arch.resv_ram >= base[0] &&
661 gd->arch.resv_ram < base[0] + size[0])
662 size[0] = gd->arch.resv_ram - base[0];
663 else if (gd->arch.resv_ram >= base[1] &&
664 gd->arch.resv_ram < base[1] + size[1])
665 size[1] = gd->arch.resv_ram - base[1];
666 else if (gd->arch.resv_ram >= base[2] &&
667 gd->arch.resv_ram < base[2] + size[2])
668 size[2] = gd->arch.resv_ram - base[2];
671 if (mc_memory_base != 0) {
672 for (i = 0; i <= total_memory_banks; i++) {
673 if (base[i] == 0 && size[i] == 0) {
674 base[i] = mc_memory_base;
675 size[i] = mc_memory_size;
681 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
684 fsl_fdt_fixup_dr_usb(blob, bd);
687 #ifdef CONFIG_FSL_MC_ENET
688 fdt_fsl_mc_fixup_iommu_map_entry(blob);
689 fdt_fixup_board_enet(blob);
691 fdt_fixup_icid(blob);
697 void qixis_dump_switch(void)
701 QIXIS_WRITE(cms[0], 0x00);
702 nr_of_cfgsw = QIXIS_READ(cms[1]);
704 puts("DIP switch settings dump:\n");
705 for (i = 1; i <= nr_of_cfgsw; i++) {
706 QIXIS_WRITE(cms[0], i);
707 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));