1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2020 NXP
7 #include <clock_legacy.h>
9 #include <dm/platform_data/serial_pl01x.h>
17 #include <fdt_support.h>
18 #include <linux/libfdt.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <env_internal.h>
21 #include <efi_loader.h>
22 #include <asm/arch/mmu.h>
24 #include <asm/arch/clock.h>
25 #include <asm/arch/config.h>
26 #include <asm/arch/fsl_serdes.h>
27 #include <asm/arch/soc.h>
28 #include "../common/qixis.h"
29 #include "../common/vid.h"
30 #include <fsl_immap.h>
31 #include <asm/arch-fsl-layerscape/fsl_icid.h>
34 #include "../common/emc2305.h"
37 #ifdef CONFIG_TARGET_LX2160AQDS
38 #define CFG_MUX_I2C_SDHC(reg, value) ((reg & 0x3f) | value)
39 #define SET_CFG_MUX1_SDHC1_SDHC(reg) (reg & 0x3f)
40 #define SET_CFG_MUX2_SDHC1_SPI(reg, value) ((reg & 0xcf) | value)
41 #define SET_CFG_MUX3_SDHC1_SPI(reg, value) ((reg & 0xf8) | value)
42 #define SET_CFG_MUX_SDHC2_DSPI(reg, value) ((reg & 0xf8) | value)
43 #define SET_CFG_MUX1_SDHC1_DSPI(reg, value) ((reg & 0x3f) | value)
44 #define SDHC1_BASE_PMUX_DSPI 2
45 #define SDHC2_BASE_PMUX_DSPI 2
46 #define IIC5_PMUX_SPI3 3
47 #endif /* CONFIG_TARGET_LX2160AQDS */
49 DECLARE_GLOBAL_DATA_PTR;
51 static struct pl01x_serial_platdata serial0 = {
52 #if CONFIG_CONS_INDEX == 0
53 .base = CONFIG_SYS_SERIAL0,
54 #elif CONFIG_CONS_INDEX == 1
55 .base = CONFIG_SYS_SERIAL1,
57 #error "Unsupported console index value."
62 U_BOOT_DEVICE(nxp_serial0) = {
63 .name = "serial_pl01x",
67 static struct pl01x_serial_platdata serial1 = {
68 .base = CONFIG_SYS_SERIAL1,
72 U_BOOT_DEVICE(nxp_serial1) = {
73 .name = "serial_pl01x",
77 int select_i2c_ch_pca9547(u8 ch)
82 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
86 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
88 ret = dm_i2c_write(dev, 0, &ch, 1);
91 puts("PCA: failed to select proper channel\n");
98 static void uart_get_clock(void)
100 serial0.clock = get_serial_clock();
101 serial1.clock = get_serial_clock();
104 int board_early_init_f(void)
106 #ifdef CONFIG_SYS_I2C_EARLY_INIT
109 /* get required clock for UART IP */
112 #ifdef CONFIG_EMC2305
113 select_i2c_ch_pca9547(I2C_MUX_CH_EMC2305);
115 set_fan_speed(I2C_EMC2305_PWM);
116 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
119 fsl_lsch3_early_init_f();
123 #ifdef CONFIG_OF_BOARD_FIXUP
124 int board_fix_fdt(void *fdt)
126 char *reg_names, *reg_name;
127 int names_len, old_name_len, new_name_len, remaining_names_len;
131 } reg_names_map[] = {
133 { "pf_ctrl", "ctrl" }
137 if (IS_SVR_REV(get_svr(), 1, 0))
140 off = fdt_node_offset_by_compatible(fdt, -1, "fsl,lx2160a-pcie");
141 while (off != -FDT_ERR_NOTFOUND) {
142 fdt_setprop(fdt, off, "compatible", "fsl,ls-pcie",
143 strlen("fsl,ls-pcie") + 1);
145 reg_names = (char *)fdt_getprop(fdt, off, "reg-names",
150 reg_name = reg_names;
151 remaining_names_len = names_len - (reg_name - reg_names);
152 while ((i < ARRAY_SIZE(reg_names_map)) && remaining_names_len) {
153 old_name_len = strlen(reg_names_map[i].old_str);
154 new_name_len = strlen(reg_names_map[i].new_str);
155 if (memcmp(reg_name, reg_names_map[i].old_str,
156 old_name_len) == 0) {
157 /* first only leave required bytes for new_str
158 * and copy rest of the string after it
160 memcpy(reg_name + new_name_len,
161 reg_name + old_name_len,
162 remaining_names_len - old_name_len);
163 /* Now copy new_str */
164 memcpy(reg_name, reg_names_map[i].new_str,
166 names_len -= old_name_len;
167 names_len += new_name_len;
171 reg_name = memchr(reg_name, '\0', remaining_names_len);
177 remaining_names_len = names_len -
178 (reg_name - reg_names);
181 fdt_setprop(fdt, off, "reg-names", reg_names, names_len);
182 off = fdt_node_offset_by_compatible(fdt, off,
190 #if defined(CONFIG_TARGET_LX2160AQDS)
191 void esdhc_dspi_status_fixup(void *blob)
193 const char esdhc0_path[] = "/soc/esdhc@2140000";
194 const char esdhc1_path[] = "/soc/esdhc@2150000";
195 const char dspi0_path[] = "/soc/spi@2100000";
196 const char dspi1_path[] = "/soc/spi@2110000";
197 const char dspi2_path[] = "/soc/spi@2120000";
199 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
204 /* Check RCW field sdhc1_base_pmux to enable/disable
205 * esdhc0/dspi0 DT node
207 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
208 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
209 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
211 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
212 do_fixup_by_path(blob, dspi0_path, "status", "okay",
214 do_fixup_by_path(blob, esdhc0_path, "status", "disabled",
215 sizeof("disabled"), 1);
217 do_fixup_by_path(blob, esdhc0_path, "status", "okay",
219 do_fixup_by_path(blob, dspi0_path, "status", "disabled",
220 sizeof("disabled"), 1);
223 /* Check RCW field sdhc2_base_pmux to enable/disable
224 * esdhc1/dspi1 DT node
226 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
227 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
228 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
230 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
231 do_fixup_by_path(blob, dspi1_path, "status", "okay",
233 do_fixup_by_path(blob, esdhc1_path, "status", "disabled",
234 sizeof("disabled"), 1);
236 do_fixup_by_path(blob, esdhc1_path, "status", "okay",
238 do_fixup_by_path(blob, dspi1_path, "status", "disabled",
239 sizeof("disabled"), 1);
242 /* Check RCW field IIC5 to enable dspi2 DT node */
243 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
244 & FSL_CHASSIS3_IIC5_PMUX_MASK;
245 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
247 if (iic5_pmux == IIC5_PMUX_SPI3)
248 do_fixup_by_path(blob, dspi2_path, "status", "okay",
251 do_fixup_by_path(blob, dspi2_path, "status", "disabled",
252 sizeof("disabled"), 1);
256 int esdhc_status_fixup(void *blob, const char *compat)
258 #if defined(CONFIG_TARGET_LX2160AQDS)
259 /* Enable esdhc and dspi DT nodes based on RCW fields */
260 esdhc_dspi_status_fixup(blob);
262 /* Enable both esdhc DT nodes for LX2160ARDB */
263 do_fixup_by_compat(blob, compat, "status", "okay",
269 #if defined(CONFIG_VID)
270 int i2c_multiplexer_select_vid_channel(u8 channel)
272 return select_i2c_ch_pca9547(channel);
275 int init_func_vid(void)
277 if (adjust_vdd(0) < 0)
278 printf("core voltage not adjusted\n");
286 enum boot_src src = get_boot_src();
289 #ifdef CONFIG_TARGET_LX2160AQDS
291 static const char *const freq[] = {"100", "125", "156.25",
292 "161.13", "322.26", "", "", "",
293 "", "", "", "", "", "", "",
294 "100 separate SSCG"};
298 #ifdef CONFIG_TARGET_LX2160AQDS
299 printf("Board: %s-QDS, ", buf);
301 printf("Board: %s-RDB, ", buf);
304 sw = QIXIS_READ(arch);
305 printf("Board version: %c, boot from ", (sw & 0xf) - 1 + 'A');
307 if (src == BOOT_SOURCE_SD_MMC) {
309 } else if (src == BOOT_SOURCE_SD_MMC2) {
312 sw = QIXIS_READ(brdcfg[0]);
313 sw = (sw >> QIXIS_XMAP_SHIFT) & QIXIS_XMAP_MASK;
317 puts("FlexSPI DEV#0\n");
320 puts("FlexSPI DEV#1\n");
324 puts("FlexSPI EMU\n");
327 printf("invalid setting, xmap: %d\n", sw);
331 #ifdef CONFIG_TARGET_LX2160AQDS
332 printf("FPGA: v%d (%s), build %d",
333 (int)QIXIS_READ(scver), qixis_read_tag(buf),
334 (int)qixis_read_minor());
335 /* the timestamp string contains "\n" at the end */
336 printf(" on %s", qixis_read_time(buf));
338 puts("SERDES1 Reference : ");
339 sw = QIXIS_READ(brdcfg[2]);
341 printf("Clock1 = %sMHz ", freq[clock]);
343 printf("Clock2 = %sMHz", freq[clock]);
345 sw = QIXIS_READ(brdcfg[3]);
346 puts("\nSERDES2 Reference : ");
348 printf("Clock1 = %sMHz ", freq[clock]);
350 printf("Clock2 = %sMHz", freq[clock]);
352 sw = QIXIS_READ(brdcfg[12]);
353 puts("\nSERDES3 Reference : ");
355 printf("Clock1 = %sMHz Clock2 = %sMHz\n", freq[clock], freq[clock]);
357 printf("FPGA: v%d.%d\n", QIXIS_READ(scver), QIXIS_READ(tagdata));
359 puts("SERDES1 Reference: Clock1 = 161.13MHz Clock2 = 161.13MHz\n");
360 puts("SERDES2 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
361 puts("SERDES3 Reference: Clock1 = 100MHz Clock2 = 100MHz\n");
366 #ifdef CONFIG_TARGET_LX2160AQDS
368 * implementation of CONFIG_ESDHC_DETECT_QUIRK Macro.
370 u8 qixis_esdhc_detect_quirk(void)
372 /* for LX2160AQDS res1[1] @ offset 0x1A is SDHC1 Control/Status (SDHC1)
374 * Specifies the type of card installed in the SDHC1 adapter slot.
376 * 001= eMMC V4.5 adapter is installed.
377 * 010= SD/MMC 3.3V adapter is installed.
378 * 011= eMMC V4.4 adapter is installed.
379 * 100= eMMC V5.0 adapter is installed.
380 * 101= MMC card/Legacy (3.3V) adapter is installed.
381 * 110= SDCard V2/V3 adapter installed.
382 * 111= no adapter is installed.
384 return ((QIXIS_READ(res1[1]) & QIXIS_SDID_MASK) !=
385 QIXIS_ESDHC_NO_ADAPTER);
388 int config_board_mux(void)
390 u8 reg11, reg5, reg13;
391 struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
396 /* Routes {I2C2_SCL, I2C2_SDA} to SDHC1 as {SDHC1_CD_B, SDHC1_WP}.
397 * Routes {I2C3_SCL, I2C3_SDA} to CAN transceiver as {CAN1_TX,CAN1_RX}.
398 * Routes {I2C4_SCL, I2C4_SDA} to CAN transceiver as {CAN2_TX,CAN2_RX}.
399 * Qixis and remote systems are isolated from the I2C1 bus.
400 * Processor connections are still available.
401 * SPI2 CS2_B controls EN25S64 SPI memory device.
402 * SPI3 CS2_B controls EN25S64 SPI memory device.
403 * EC2 connects to PHY #2 using RGMII protocol.
404 * CLK_OUT connects to FPGA for clock measurement.
407 reg5 = QIXIS_READ(brdcfg[5]);
408 reg5 = CFG_MUX_I2C_SDHC(reg5, 0x40);
409 QIXIS_WRITE(brdcfg[5], reg5);
411 /* Check RCW field sdhc1_base_pmux
412 * esdhc0 : sdhc1_base_pmux = 0
413 * dspi0 : sdhc1_base_pmux = 2
415 sdhc1_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
416 & FSL_CHASSIS3_SDHC1_BASE_PMUX_MASK;
417 sdhc1_base_pmux >>= FSL_CHASSIS3_SDHC1_BASE_PMUX_SHIFT;
419 if (sdhc1_base_pmux == SDHC1_BASE_PMUX_DSPI) {
420 reg11 = QIXIS_READ(brdcfg[11]);
421 reg11 = SET_CFG_MUX1_SDHC1_DSPI(reg11, 0x40);
422 QIXIS_WRITE(brdcfg[11], reg11);
424 /* - Routes {SDHC1_CMD, SDHC1_CLK } to SDHC1 adapter slot.
425 * {SDHC1_DAT3, SDHC1_DAT2} to SDHC1 adapter slot.
426 * {SDHC1_DAT1, SDHC1_DAT0} to SDHC1 adapter slot.
428 reg11 = QIXIS_READ(brdcfg[11]);
429 reg11 = SET_CFG_MUX1_SDHC1_SDHC(reg11);
430 QIXIS_WRITE(brdcfg[11], reg11);
433 /* Check RCW field sdhc2_base_pmux
434 * esdhc1 : sdhc2_base_pmux = 0 (default)
435 * dspi1 : sdhc2_base_pmux = 2
437 sdhc2_base_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR13_REGSR - 1])
438 & FSL_CHASSIS3_SDHC2_BASE_PMUX_MASK;
439 sdhc2_base_pmux >>= FSL_CHASSIS3_SDHC2_BASE_PMUX_SHIFT;
441 if (sdhc2_base_pmux == SDHC2_BASE_PMUX_DSPI) {
442 reg13 = QIXIS_READ(brdcfg[13]);
443 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x01);
444 QIXIS_WRITE(brdcfg[13], reg13);
446 reg13 = QIXIS_READ(brdcfg[13]);
447 reg13 = SET_CFG_MUX_SDHC2_DSPI(reg13, 0x00);
448 QIXIS_WRITE(brdcfg[13], reg13);
451 /* Check RCW field IIC5 to enable dspi2 DT nodei
454 iic5_pmux = gur_in32(&gur->rcwsr[FSL_CHASSIS3_RCWSR12_REGSR - 1])
455 & FSL_CHASSIS3_IIC5_PMUX_MASK;
456 iic5_pmux >>= FSL_CHASSIS3_IIC5_PMUX_SHIFT;
458 if (iic5_pmux == IIC5_PMUX_SPI3) {
459 /* - Routes {SDHC1_DAT4} to SPI3 devices as {SPI3_M_CS0_B}. */
460 reg11 = QIXIS_READ(brdcfg[11]);
461 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x10);
462 QIXIS_WRITE(brdcfg[11], reg11);
464 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} nowhere.
465 * {SDHC1_DAT7, SDHC1_DS } to {nothing, SPI3_M0_CLK }.
466 * {I2C5_SCL, I2C5_SDA } to {SPI3_M0_MOSI, SPI3_M0_MISO}.
468 reg11 = QIXIS_READ(brdcfg[11]);
469 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x01);
470 QIXIS_WRITE(brdcfg[11], reg11);
472 /* Routes {SDHC1_DAT4} to SDHC1 adapter slot */
473 reg11 = QIXIS_READ(brdcfg[11]);
474 reg11 = SET_CFG_MUX2_SDHC1_SPI(reg11, 0x00);
475 QIXIS_WRITE(brdcfg[11], reg11);
477 /* - Routes {SDHC1_DAT5, SDHC1_DAT6} to SDHC1 adapter slot.
478 * {SDHC1_DAT7, SDHC1_DS } to SDHC1 adapter slot.
479 * {I2C5_SCL, I2C5_SDA } to SDHC1 adapter slot.
481 reg11 = QIXIS_READ(brdcfg[11]);
482 reg11 = SET_CFG_MUX3_SDHC1_SPI(reg11, 0x00);
483 QIXIS_WRITE(brdcfg[11], reg11);
488 #elif defined(CONFIG_TARGET_LX2160ARDB)
489 int config_board_mux(void)
493 brdcfg = QIXIS_READ(brdcfg[4]);
494 /* The BRDCFG4 register controls general board configuration.
495 *|-------------------------------------------|
497 *|-------------------------------------------|
498 *|5 | CAN I/O Enable (net CFG_CAN_EN_B):|
499 *|CAN_EN | 0= CAN transceivers are disabled. |
500 *| | 1= CAN transceivers are enabled. |
501 *|-------------------------------------------|
503 brdcfg |= BIT_MASK(5);
504 QIXIS_WRITE(brdcfg[4], brdcfg);
509 int config_board_mux(void)
515 unsigned long get_board_sys_clk(void)
517 #ifdef CONFIG_TARGET_LX2160AQDS
518 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
520 switch (sysclk_conf & 0x03) {
521 case QIXIS_SYSCLK_100:
523 case QIXIS_SYSCLK_125:
525 case QIXIS_SYSCLK_133:
534 unsigned long get_board_ddr_clk(void)
536 #ifdef CONFIG_TARGET_LX2160AQDS
537 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
539 switch ((ddrclk_conf & 0x30) >> 4) {
540 case QIXIS_DDRCLK_100:
542 case QIXIS_DDRCLK_125:
544 case QIXIS_DDRCLK_133:
555 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
556 u32 __iomem *irq_ccsr = (u32 __iomem *)ISC_BASE;
558 #ifdef CONFIG_ENV_IS_NOWHERE
559 gd->env_addr = (ulong)&default_environment[0];
562 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
564 #if defined(CONFIG_FSL_MC_ENET) && defined(CONFIG_TARGET_LX2160ARDB)
565 /* invert AQR107 IRQ pins polarity */
566 out_le32(irq_ccsr + IRQCR_OFFSET / 4, AQR107_IRQ_MASK);
569 #ifdef CONFIG_FSL_CAAM
576 void detail_board_ddr_info(void)
582 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++)
583 ddr_size += gd->bd->bi_dram[i].size;
584 print_size(ddr_size, "");
588 #ifdef CONFIG_MISC_INIT_R
589 int misc_init_r(void)
597 #ifdef CONFIG_FSL_MC_ENET
598 extern int fdt_fixup_board_phy(void *fdt);
600 void fdt_fixup_board_enet(void *fdt)
604 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
607 offset = fdt_path_offset(fdt, "/fsl-mc");
610 printf("%s: fsl-mc node not found in device tree (error %d)\n",
615 if (get_mc_boot_status() == 0 &&
616 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0)) {
617 fdt_status_okay(fdt, offset);
618 fdt_fixup_board_phy(fdt);
620 fdt_status_fail(fdt, offset);
624 void board_quiesce_devices(void)
626 fsl_mc_ldpaa_exit(gd->bd);
630 #ifdef CONFIG_OF_BOARD_SETUP
632 int ft_board_setup(void *blob, bd_t *bd)
635 u16 mc_memory_bank = 0;
639 u64 mc_memory_base = 0;
640 u64 mc_memory_size = 0;
641 u16 total_memory_banks;
643 ft_cpu_setup(blob, bd);
645 fdt_fixup_mc_ddr(&mc_memory_base, &mc_memory_size);
647 if (mc_memory_base != 0)
650 total_memory_banks = CONFIG_NR_DRAM_BANKS + mc_memory_bank;
652 base = calloc(total_memory_banks, sizeof(u64));
653 size = calloc(total_memory_banks, sizeof(u64));
655 /* fixup DT for the three GPP DDR banks */
656 for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) {
657 base[i] = gd->bd->bi_dram[i].start;
658 size[i] = gd->bd->bi_dram[i].size;
661 #ifdef CONFIG_RESV_RAM
662 /* reduce size if reserved memory is within this bank */
663 if (gd->arch.resv_ram >= base[0] &&
664 gd->arch.resv_ram < base[0] + size[0])
665 size[0] = gd->arch.resv_ram - base[0];
666 else if (gd->arch.resv_ram >= base[1] &&
667 gd->arch.resv_ram < base[1] + size[1])
668 size[1] = gd->arch.resv_ram - base[1];
669 else if (gd->arch.resv_ram >= base[2] &&
670 gd->arch.resv_ram < base[2] + size[2])
671 size[2] = gd->arch.resv_ram - base[2];
674 if (mc_memory_base != 0) {
675 for (i = 0; i <= total_memory_banks; i++) {
676 if (base[i] == 0 && size[i] == 0) {
677 base[i] = mc_memory_base;
678 size[i] = mc_memory_size;
684 fdt_fixup_memory_banks(blob, base, size, total_memory_banks);
687 fsl_fdt_fixup_dr_usb(blob, bd);
690 #ifdef CONFIG_FSL_MC_ENET
691 fdt_fsl_mc_fixup_iommu_map_entry(blob);
692 fdt_fixup_board_enet(blob);
694 fdt_fixup_icid(blob);
700 void qixis_dump_switch(void)
704 QIXIS_WRITE(cms[0], 0x00);
705 nr_of_cfgsw = QIXIS_READ(cms[1]);
707 puts("DIP switch settings dump:\n");
708 for (i = 1; i <= nr_of_cfgsw; i++) {
709 QIXIS_WRITE(cms[0], i);
710 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));