1 // SPDX-License-Identifier: GPL-2.0+
9 #include <fdt_support.h>
19 #include <asm/arch/fsl_serdes.h>
20 #include <fsl-mc/fsl_mc.h>
21 #include <fsl-mc/ldpaa_wriop.h>
23 DECLARE_GLOBAL_DATA_PTR;
25 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
30 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
31 phy_id = (phy_reg & 0xffff) << 16;
33 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
34 phy_id |= (phy_reg & 0xffff);
36 if (phy_id == PHY_UID_IN112525_S03)
42 int board_eth_init(bd_t *bis)
44 #if defined(CONFIG_FSL_MC_ENET)
45 struct memac_mdio_info mdio_info;
46 struct memac_mdio_controller *reg;
49 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
52 srds_s1 = in_le32(&gur->rcwsr[28]) &
53 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
54 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
56 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
58 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
60 /* Register the EMI 1 */
61 fm_memac_mdio_init(bis, &mdio_info);
63 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
65 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
67 /* Register the EMI 2 */
68 fm_memac_mdio_init(bis, &mdio_info);
70 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
73 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
75 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
77 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
79 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
80 wriop_set_phy_address(WRIOP1_DPMAC5, 0,
82 wriop_set_phy_address(WRIOP1_DPMAC6, 0,
85 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
87 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
92 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
94 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
96 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
98 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
100 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
102 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
104 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
105 wriop_set_phy_address(WRIOP1_DPMAC5, 0,
107 wriop_set_phy_address(WRIOP1_DPMAC6, 0,
110 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
112 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
117 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
122 for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
123 interface = wriop_get_enet_if(i);
125 case PHY_INTERFACE_MODE_XGMII:
126 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
127 wriop_set_mdio(i, dev);
129 case PHY_INTERFACE_MODE_25G_AUI:
130 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
131 wriop_set_mdio(i, dev);
133 case PHY_INTERFACE_MODE_XLAUI:
134 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
135 wriop_set_mdio(i, dev);
141 for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
142 interface = wriop_get_enet_if(i);
144 case PHY_INTERFACE_MODE_RGMII:
145 case PHY_INTERFACE_MODE_RGMII_ID:
146 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
147 wriop_set_mdio(i, dev);
156 #endif /* CONFIG_FSL_MC_ENET */
158 #ifdef CONFIG_PHY_AQUANTIA
160 * Export functions to be used by AQ firmware
163 gd->jt->strcpy = strcpy;
164 gd->jt->mdelay = mdelay;
165 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
166 gd->jt->phy_find_by_mask = phy_find_by_mask;
167 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
168 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
170 return pci_eth_init(bis);
173 #if defined(CONFIG_RESET_PHY_R)
176 #if defined(CONFIG_FSL_MC_ENET)
180 #endif /* CONFIG_RESET_PHY_R */
182 int fdt_fixup_board_phy(void *fdt)
190 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
191 if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
192 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
195 mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
197 if (mdio_offset < 0) {
198 printf("mdio@0x8B9700 node not found in dts\n");
202 ret = fdt_setprop_string(fdt, mdio_offset, "status",
205 printf("Could not set disable mdio@0x8B97000 %s\n",