1 // SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/fsl_serdes.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <fsl-mc/ldpaa_wriop.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 static bool get_inphi_phy_id(struct mii_dev *bus, int addr, int devad)
29 phy_reg = bus->read(bus, addr, devad, MII_PHYSID1);
30 phy_id = (phy_reg & 0xffff) << 16;
32 phy_reg = bus->read(bus, addr, devad, MII_PHYSID2);
33 phy_id |= (phy_reg & 0xffff);
35 if (phy_id == PHY_UID_IN112525_S03)
41 int board_eth_init(bd_t *bis)
43 #if defined(CONFIG_FSL_MC_ENET)
44 struct memac_mdio_info mdio_info;
45 struct memac_mdio_controller *reg;
48 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
51 srds_s1 = in_le32(&gur->rcwsr[28]) &
52 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
53 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
55 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
57 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
59 /* Register the EMI 1 */
60 fm_memac_mdio_init(bis, &mdio_info);
62 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
64 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
66 /* Register the EMI 2 */
67 fm_memac_mdio_init(bis, &mdio_info);
69 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
72 wriop_set_phy_address(WRIOP1_DPMAC2, 0,
74 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
76 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
78 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
79 wriop_set_phy_address(WRIOP1_DPMAC5, 0,
81 wriop_set_phy_address(WRIOP1_DPMAC6, 0,
84 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
86 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
91 wriop_set_phy_address(WRIOP1_DPMAC7, 0,
93 wriop_set_phy_address(WRIOP1_DPMAC8, 0,
95 wriop_set_phy_address(WRIOP1_DPMAC9, 0,
97 wriop_set_phy_address(WRIOP1_DPMAC10, 0,
99 wriop_set_phy_address(WRIOP1_DPMAC3, 0,
101 wriop_set_phy_address(WRIOP1_DPMAC4, 0,
103 if (get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
104 wriop_set_phy_address(WRIOP1_DPMAC5, 0,
106 wriop_set_phy_address(WRIOP1_DPMAC6, 0,
109 wriop_set_phy_address(WRIOP1_DPMAC17, 0,
111 wriop_set_phy_address(WRIOP1_DPMAC18, 0,
116 printf("SerDes1 protocol 0x%x is not supported on LX2160ARDB\n",
121 for (i = WRIOP1_DPMAC2; i <= WRIOP1_DPMAC10; i++) {
122 interface = wriop_get_enet_if(i);
124 case PHY_INTERFACE_MODE_XGMII:
125 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
126 wriop_set_mdio(i, dev);
128 case PHY_INTERFACE_MODE_25G_AUI:
129 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
130 wriop_set_mdio(i, dev);
132 case PHY_INTERFACE_MODE_XLAUI:
133 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
134 wriop_set_mdio(i, dev);
140 for (i = WRIOP1_DPMAC17; i <= WRIOP1_DPMAC18; i++) {
141 interface = wriop_get_enet_if(i);
143 case PHY_INTERFACE_MODE_RGMII:
144 case PHY_INTERFACE_MODE_RGMII_ID:
145 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
146 wriop_set_mdio(i, dev);
155 #endif /* CONFIG_FSL_MC_ENET */
157 #ifdef CONFIG_PHY_AQUANTIA
159 * Export functions to be used by AQ firmware
162 gd->jt->strcpy = strcpy;
163 gd->jt->mdelay = mdelay;
164 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
165 gd->jt->phy_find_by_mask = phy_find_by_mask;
166 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
167 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
169 return pci_eth_init(bis);
172 #if defined(CONFIG_RESET_PHY_R)
175 #if defined(CONFIG_FSL_MC_ENET)
179 #endif /* CONFIG_RESET_PHY_R */
181 int fdt_fixup_board_phy(void *fdt)
189 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
190 if (!get_inphi_phy_id(dev, INPHI_PHY_ADDR1, MDIO_MMD_VEND1)) {
191 mdio_offset = fdt_path_offset(fdt, "/soc/mdio@0x8B97000");
194 mdio_offset = fdt_path_offset(fdt, "/mdio@0x8B97000");
196 if (mdio_offset < 0) {
197 printf("mdio@0x8B9700 node not found in dts\n");
201 ret = fdt_setprop_string(fdt, mdio_offset, "status",
204 printf("Could not set disable mdio@0x8B97000 %s\n",