1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
20 #include <asm/arch/fsl_serdes.h>
21 #include <fsl-mc/fsl_mc.h>
22 #include <fsl-mc/ldpaa_wriop.h>
24 #include "../common/qixis.h"
26 DECLARE_GLOBAL_DATA_PTR;
29 #define EMI1 1 /* Mdio Bus 1 */
30 #define EMI2 2 /* Mdio Bus 2 */
32 #if defined(CONFIG_FSL_MC_ENET)
48 struct lx2160a_qds_mdio {
49 enum io_slot ioslot : 4;
51 struct mii_dev *realbus;
54 /* structure explaining the phy configuration on 8 lanes of a serdes*/
55 struct serdes_phy_config {
56 u8 serdes; /* serdes protocol */
59 /* -1 terminated array */
60 int phy_address[WRIOP_MAX_PHY_NUM + 1];
63 } phy_config[SRDS_MAX_LANES];
66 /* Table defining the phy configuration on 8 lanes of a serdes.
67 * Various assumptions have been made while defining this table.
68 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
69 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
70 * And also that this card is connected to IO Slot 1 (could have been connected
71 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
72 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
73 * used in serdes1 protocol 19 (could have selected MDIO 2)
74 * To override these settings "dpmac" environment variable can be used after
75 * defining "dpmac_override" in hwconfig environment variable.
76 * This table has limited serdes protocol entries. It can be expanded as per
79 static const struct serdes_phy_config serdes1_phy_config[] = {
80 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
82 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
84 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
86 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
88 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
90 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
92 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
94 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
96 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
98 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
100 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
102 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
103 EMI1, IO_SLOT_2} } },
105 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
107 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
108 EMI1, IO_SLOT_2} } },
109 {14, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
110 EMI1, IO_SLOT_1} } },
111 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
113 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
114 EMI1, IO_SLOT_1} } },
115 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
117 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
119 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
121 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
122 EMI1, IO_SLOT_1} } },
123 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
125 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
127 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
129 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
131 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
132 EMI1, IO_SLOT_6} } },
133 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
135 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
139 static const struct serdes_phy_config serdes2_phy_config[] = {
143 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
145 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
147 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
149 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
151 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
153 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
154 EMI1, IO_SLOT_8} } },
157 static const struct serdes_phy_config serdes3_phy_config[] = {
163 const struct phy_config *get_phy_config(u8 serdes,
164 const struct serdes_phy_config *table,
169 for (i = 0; i < table_size; i++) {
170 if (table[i].serdes == serdes)
171 return table[i].phy_config;
177 /* BRDCFG4 controls EMI routing for the board.
179 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
180 * EMI1 00= On-board PHY #1
181 * 01= On-board PHY #2
183 * 11= Slots 1..8 multiplexer and translator.
184 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
193 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
194 * EMI2 000= Slot #1 (secondary EMI)
195 * 001= Slot #2 (secondary EMI)
196 * 010= Slot #3 (secondary EMI)
197 * 011= Slot #4 (secondary EMI)
198 * 100= Slot #5 (secondary EMI)
199 * 101= Slot #6 (secondary EMI)
200 * 110= Slot #7 (secondary EMI)
201 * 111= Slot #8 (secondary EMI)
203 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
205 switch (realbusnum) {
213 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
217 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
223 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
225 u8 brdcfg4, mux_val, reg;
227 brdcfg4 = QIXIS_READ(brdcfg[4]);
229 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
231 switch (priv->realbusnum) {
233 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
237 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
243 QIXIS_WRITE(brdcfg[4], brdcfg4);
246 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
247 int devad, int regnum)
249 struct lx2160a_qds_mdio *priv = bus->priv;
251 lx2160a_qds_mux_mdio(priv);
253 return priv->realbus->read(priv->realbus, addr, devad, regnum);
256 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
257 int regnum, u16 value)
259 struct lx2160a_qds_mdio *priv = bus->priv;
261 lx2160a_qds_mux_mdio(priv);
263 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
266 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
268 struct lx2160a_qds_mdio *priv = bus->priv;
270 return priv->realbus->reset(priv->realbus);
273 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
275 struct lx2160a_qds_mdio *pmdio;
277 /*should be within MDIO_NAME_LEN*/
278 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
280 if (realbusnum == EMI2) {
281 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
282 printf("invalid ioslot %d\n", ioslot);
285 } else if (realbusnum == EMI1) {
286 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
287 printf("invalid ioslot %d\n", ioslot);
291 printf("not supported real mdio bus %d\n", realbusnum);
295 if (ioslot == EMI1_RGMII1)
296 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
297 else if (ioslot == EMI1_RGMII2)
298 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
300 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
302 bus = miiphy_get_dev_by_name(dummy_mdio_name);
309 printf("Failed to allocate %s bus\n", dummy_mdio_name);
313 pmdio = malloc(sizeof(*pmdio));
315 printf("Failed to allocate %s private data\n", dummy_mdio_name);
320 switch (realbusnum) {
323 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
327 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
331 if (!pmdio->realbus) {
332 printf("No real mdio bus num %d found\n", realbusnum);
338 pmdio->realbusnum = realbusnum;
339 pmdio->ioslot = ioslot;
340 bus->read = lx2160a_qds_mdio_read;
341 bus->write = lx2160a_qds_mdio_write;
342 bus->reset = lx2160a_qds_mdio_reset;
343 strcpy(bus->name, dummy_mdio_name);
346 if (!mdio_register(bus))
349 printf("No bus with name %s\n", dummy_mdio_name);
355 static inline void do_phy_config(const struct phy_config *phy_config)
358 int i, phy_num, phy_address;
360 for (i = 0; i < SRDS_MAX_LANES; i++) {
361 if (!phy_config[i].dpmacid)
365 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
367 phy_address = phy_config[i].phy_address[phy_num];
368 if (phy_address == -1)
370 wriop_set_phy_address(phy_config[i].dpmacid,
371 phy_num, phy_address);
373 /*Register the muxing front-ends to the MDIO buses*/
374 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
375 phy_config[i].ioslot);
377 printf("could not get bus for mdio %d ioslot %d\n",
378 phy_config[i].mdio_bus,
379 phy_config[i].ioslot);
381 wriop_set_mdio(phy_config[i].dpmacid, bus);
385 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
390 u8 realbusnum, ioslot;
393 char *phystr = "phy00";
395 /*search phy in dpmac arg*/
396 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
397 sprintf(phystr, "phy%d", phy_num + 1);
398 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
400 /*look for phy instead of phy1*/
402 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
408 if (len != 4 || strncmp(ret, "0x", 2))
409 printf("invalid phy format in %s variable.\n"
410 "specify phy%d for %s in hex format e.g. 0x12\n",
411 env_dpmac, phy_num + 1, arg_dpmacid);
413 wriop_set_phy_address(dpmac, phy_num,
414 simple_strtoul(ret, NULL, 16));
417 /*search mdio in dpmac arg*/
418 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
420 realbusnum = *ret - '0';
422 realbusnum = EMI_NONE;
425 /*search io in dpmac arg*/
426 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
430 ioslot = IO_SLOT_NONE;
431 /*Register the muxing front-ends to the MDIO buses*/
432 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
434 printf("could not get bus for mdio %d ioslot %d\n",
437 wriop_set_mdio(dpmac, bus);
443 int board_eth_init(bd_t *bis)
445 #if defined(CONFIG_FSL_MC_ENET)
446 struct memac_mdio_info mdio_info;
447 struct memac_mdio_controller *regs;
451 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
454 const struct phy_config *phy_config;
455 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
456 u32 srds_s1, srds_s2, srds_s3;
458 srds_s1 = in_le32(&gur->rcwsr[28]) &
459 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
460 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
462 srds_s2 = in_le32(&gur->rcwsr[28]) &
463 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
464 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
466 srds_s3 = in_le32(&gur->rcwsr[28]) &
467 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
468 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
470 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
472 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
473 mdio_info.regs = regs;
474 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
476 /*Register the EMI 1*/
477 fm_memac_mdio_init(bis, &mdio_info);
479 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
480 mdio_info.regs = regs;
481 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
483 /*Register the EMI 2*/
484 fm_memac_mdio_init(bis, &mdio_info);
486 /* "dpmac" environment variable can be used after
487 * defining "dpmac_override" in hwconfig environment variable.
489 if (hwconfig("dpmac_override")) {
490 env_dpmac = env_get("dpmac");
492 ret = hwconfig_arg_f("srds", &len, env_dpmac);
494 if (strncmp(ret, srds, strlen(srds))) {
495 printf("SERDES configuration changed.\n"
496 "previous: %.*s, current: %s.\n"
497 "update dpmac variable.\n",
498 (int)len, ret, srds);
501 printf("SERDES configuration not found.\n"
502 "Please add srds:%s in dpmac variable\n",
506 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
507 /* Look for dpmac1 to dpmac24(current max) arg
508 * in dpmac environment variable
510 sprintf(dpmacid, "dpmac%d", i);
511 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
513 do_dpmac_config(i, dpmacid, env_dpmac);
516 printf("Warning: environment dpmac not found.\n"
517 "DPAA network interfaces may not work\n");
520 /*Look for phy config for serdes1 in phy config table*/
521 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
522 ARRAY_SIZE(serdes1_phy_config));
524 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
527 do_phy_config(phy_config);
529 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
530 ARRAY_SIZE(serdes2_phy_config));
532 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
535 do_phy_config(phy_config);
537 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
538 ARRAY_SIZE(serdes3_phy_config));
540 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
543 do_phy_config(phy_config);
547 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
548 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
549 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
551 printf("could not get bus for RGMII1\n");
553 wriop_set_mdio(WRIOP1_DPMAC17, bus);
556 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
557 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
558 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
560 printf("could not get bus for RGMII2\n");
562 wriop_set_mdio(WRIOP1_DPMAC18, bus);
566 #endif /* CONFIG_FMAN_ENET */
568 #ifdef CONFIG_PHY_AQUANTIA
570 * Export functions to be used by AQ firmware
573 gd->jt->strcpy = strcpy;
574 gd->jt->mdelay = mdelay;
575 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
576 gd->jt->phy_find_by_mask = phy_find_by_mask;
577 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
578 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
580 return pci_eth_init(bis);
583 #if defined(CONFIG_RESET_PHY_R)
586 #if defined(CONFIG_FSL_MC_ENET)
590 #endif /* CONFIG_RESET_PHY_R */
592 #if defined(CONFIG_FSL_MC_ENET)
593 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
597 char dpmac_str[] = "dpmacs@00";
598 const char *phy_string;
600 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
603 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
606 printf("dpmacs node not found in device tree\n");
610 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
611 debug("dpmac_str = %s\n", dpmac_str);
613 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
615 printf("%s node not found in device tree\n", dpmac_str);
619 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
621 printf("%d@%s %d\n", __LINE__, __func__, ret);
623 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
624 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
627 printf("%d@%s %d\n", __LINE__, __func__, ret);
632 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
634 char mdio_ioslot_str[] = "mdio@00";
635 struct lx2160a_qds_mdio *priv;
640 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
641 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
642 strlen("LX2160A_QDS_MDIO")))
645 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
646 priv = mii_dev->priv;
648 debug("real_bus_num = %d, ioslot = %d\n",
649 priv->realbusnum, priv->ioslot);
651 if (priv->realbusnum == EMI1)
652 reg = CONFIG_SYS_FSL_WRIOP1_MDIO1;
654 reg = CONFIG_SYS_FSL_WRIOP1_MDIO2;
656 offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg);
658 printf("mdio@%llx node not found in device tree\n", reg);
662 phandle = fdt_get_phandle(fdt, offset);
663 phandle = cpu_to_fdt32(phandle);
664 offset = fdt_node_offset_by_prop_value(fdt, -1, "mdio-parent-bus",
667 printf("mdio-mux-%d node not found in device tree\n",
668 priv->realbusnum == EMI1 ? 1 : 2);
672 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
673 if (priv->realbusnum == EMI1)
674 mux_val >>= BRDCFG4_EMI1SEL_SHIFT;
676 mux_val >>= BRDCFG4_EMI2SEL_SHIFT;
677 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
679 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
681 printf("%s node not found in device tree\n", mdio_ioslot_str);
688 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
689 struct phy_device *phy_dev, int phandle)
691 char phy_node_name[] = "ethernet-phy@00";
692 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000,";
695 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
696 debug("phy_node_name = %s\n", phy_node_name);
698 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
699 if (*subnodeoffset <= 0) {
700 printf("Could not add subnode %s inside node %s err = %s\n",
701 phy_node_name, fdt_get_name(fdt, offset, NULL),
702 fdt_strerror(*subnodeoffset));
703 return *subnodeoffset;
706 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x,",
707 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
708 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
710 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
711 phy_id_compatible_str);
713 printf("%d@%s %d\n", __LINE__, __func__, ret);
717 if (phy_dev->is_c45) {
718 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
719 "ethernet-phy-ieee802.3-c45");
721 printf("%d@%s %d\n", __LINE__, __func__, ret);
725 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
726 "ethernet-phy-ieee802.3-c22");
728 printf("%d@%s %d\n", __LINE__, __func__, ret);
733 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
735 printf("%d@%s %d\n", __LINE__, __func__, ret);
739 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
741 printf("%d@%s %d\n", __LINE__, __func__, ret);
747 fdt_del_node(fdt, *subnodeoffset);
752 int fdt_fixup_board_phy(void *fdt)
754 int fpga_offset, offset, subnodeoffset;
755 struct mii_dev *mii_dev;
756 struct list_head *mii_devs, *entry;
757 int ret, dpmac_id, phandle, i;
758 struct phy_device *phy_dev;
759 char ethname[ETH_NAME_LEN];
760 phy_interface_t phy_iface;
763 /* we know FPGA is connected to i2c0, therefore search path directly,
764 * instead of compatible property, as it saves time
766 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
769 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
771 if (fpga_offset < 0) {
772 printf("i2c@2000000/fpga node not found in device tree\n");
776 phandle = fdt_alloc_phandle(fdt);
777 mii_devs = mdio_get_list_head();
779 list_for_each(entry, mii_devs) {
780 mii_dev = list_entry(entry, struct mii_dev, link);
781 debug("mii_dev name : %s\n", mii_dev->name);
782 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
786 // Look for phy devices attached to MDIO bus muxing front end
787 // and create their entries with compatible being the device id
788 for (i = 0; i < PHY_MAX_ADDR; i++) {
789 phy_dev = mii_dev->phymap[i];
793 // TODO: use sscanf instead of loop
794 dpmac_id = WRIOP1_DPMAC1;
795 while (dpmac_id < NUM_WRIOP_PORTS) {
796 phy_iface = wriop_get_enet_if(dpmac_id);
797 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
799 phy_string_for_interface(phy_iface));
800 if (strcmp(ethname, phy_dev->dev->name) == 0)
804 if (dpmac_id == NUM_WRIOP_PORTS)
806 ret = fdt_create_phy_node(fdt, offset, i,
812 ret = fdt_fixup_dpmac_phy_handle(fdt,
815 fdt_del_node(fdt, subnodeoffset);
818 /* calculate offset again as new node addition may have
821 offset = fdt_get_ioslot_offset(fdt, mii_dev,
832 #endif // CONFIG_FSL_MC_ENET