1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2018-2019 NXP
18 #include <asm/arch/fsl_serdes.h>
19 #include <fsl-mc/fsl_mc.h>
20 #include <fsl-mc/ldpaa_wriop.h>
22 #include "../common/qixis.h"
24 DECLARE_GLOBAL_DATA_PTR;
27 #define EMI1 1 /* Mdio Bus 1 */
28 #define EMI2 2 /* Mdio Bus 2 */
30 #if defined(CONFIG_FSL_MC_ENET)
46 struct lx2160a_qds_mdio {
47 enum io_slot ioslot : 4;
49 struct mii_dev *realbus;
52 /* structure explaining the phy configuration on 8 lanes of a serdes*/
53 struct serdes_phy_config {
54 u8 serdes; /* serdes protocol */
57 /* -1 terminated array */
58 int phy_address[WRIOP_MAX_PHY_NUM + 1];
61 } phy_config[SRDS_MAX_LANES];
64 /* Table defining the phy configuration on 8 lanes of a serdes.
65 * Various assumptions have been made while defining this table.
66 * e.g. for serdes1 protocol 19 it is being assumed that X-M11-USXGMII
67 * card is being used for dpmac 3-4. (X-M12-XFI could also have been used)
68 * And also that this card is connected to IO Slot 1 (could have been connected
69 * to any of the 8 IO slots (IO slot 1 - IO slot 8)).
70 * similarly, it is also being assumed that MDIO 1 is selected on X-M7-40G card
71 * used in serdes1 protocol 19 (could have selected MDIO 2)
72 * To override these settings "dpmac" environment variable can be used after
73 * defining "dpmac_override" in hwconfig environment variable.
74 * This table has limited serdes protocol entries. It can be expanded as per
77 static const struct serdes_phy_config serdes1_phy_config[] = {
78 {3, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
80 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
82 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
84 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
86 {7, {{WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
88 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
90 {WRIOP1_DPMAC5, {AQ_PHY_ADDR3, -1},
92 {WRIOP1_DPMAC6, {AQ_PHY_ADDR4, -1},
94 {WRIOP1_DPMAC7, {SGMII_CARD_PORT1_PHY_ADDR, -1},
96 {WRIOP1_DPMAC8, {SGMII_CARD_PORT2_PHY_ADDR, -1},
98 {WRIOP1_DPMAC9, {SGMII_CARD_PORT3_PHY_ADDR, -1},
100 {WRIOP1_DPMAC10, {SGMII_CARD_PORT4_PHY_ADDR, -1},
101 EMI1, IO_SLOT_2} } },
103 {13, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
105 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
106 EMI1, IO_SLOT_2} } },
107 {15, {{WRIOP1_DPMAC1, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
109 {WRIOP1_DPMAC2, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
110 EMI1, IO_SLOT_1} } },
111 {17, {{WRIOP1_DPMAC3, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
113 {WRIOP1_DPMAC4, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
115 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
117 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
118 EMI1, IO_SLOT_1} } },
119 {19, {{WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
121 {WRIOP1_DPMAC3, {AQ_PHY_ADDR1, -1},
123 {WRIOP1_DPMAC4, {AQ_PHY_ADDR2, -1},
125 {WRIOP1_DPMAC5, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
127 {WRIOP1_DPMAC6, {INPHI_PHY_ADDR1, INPHI_PHY_ADDR2, -1},
128 EMI1, IO_SLOT_6} } },
129 {20, {{WRIOP1_DPMAC1, {CORTINA_PHY_ADDR1, -1},
131 {WRIOP1_DPMAC2, {CORTINA_PHY_ADDR1, -1},
135 static const struct serdes_phy_config serdes2_phy_config[] = {
139 {11, {{WRIOP1_DPMAC12, {SGMII_CARD_PORT2_PHY_ADDR, -1},
141 {WRIOP1_DPMAC17, {SGMII_CARD_PORT3_PHY_ADDR, -1},
143 {WRIOP1_DPMAC18, {SGMII_CARD_PORT4_PHY_ADDR, -1},
145 {WRIOP1_DPMAC16, {SGMII_CARD_PORT2_PHY_ADDR, -1},
147 {WRIOP1_DPMAC13, {SGMII_CARD_PORT3_PHY_ADDR, -1},
149 {WRIOP1_DPMAC14, {SGMII_CARD_PORT4_PHY_ADDR, -1},
150 EMI1, IO_SLOT_8} } },
153 static const struct serdes_phy_config serdes3_phy_config[] = {
159 const struct phy_config *get_phy_config(u8 serdes,
160 const struct serdes_phy_config *table,
165 for (i = 0; i < table_size; i++) {
166 if (table[i].serdes == serdes)
167 return table[i].phy_config;
173 /* BRDCFG4 controls EMI routing for the board.
175 * 7-6 EMI Interface #1 Primary Routing (CFG_MUX1_EMI1) (1.8V):
176 * EMI1 00= On-board PHY #1
177 * 01= On-board PHY #2
179 * 11= Slots 1..8 multiplexer and translator.
180 * 5-3 EMI Interface #1 Secondary Routing (CFG_MUX2_EMI1) (2.5V):
189 * 2-0 EMI Interface #2 Routing (CFG_MUX_EMI2):
190 * EMI2 000= Slot #1 (secondary EMI)
191 * 001= Slot #2 (secondary EMI)
192 * 010= Slot #3 (secondary EMI)
193 * 011= Slot #4 (secondary EMI)
194 * 100= Slot #5 (secondary EMI)
195 * 101= Slot #6 (secondary EMI)
196 * 110= Slot #7 (secondary EMI)
197 * 111= Slot #8 (secondary EMI)
199 static int lx2160a_qds_get_mdio_mux_val(u8 realbusnum, enum io_slot ioslot)
201 switch (realbusnum) {
209 return (((ioslot - 1) << BRDCFG4_EMI1SEL_SHIFT) | 0xC0);
213 return ((ioslot - 1) << BRDCFG4_EMI2SEL_SHIFT);
219 static void lx2160a_qds_mux_mdio(struct lx2160a_qds_mdio *priv)
221 u8 brdcfg4, mux_val, reg;
223 brdcfg4 = QIXIS_READ(brdcfg[4]);
225 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
227 switch (priv->realbusnum) {
229 brdcfg4 &= ~BRDCFG4_EMI1SEL_MASK;
233 brdcfg4 &= ~BRDCFG4_EMI2SEL_MASK;
239 QIXIS_WRITE(brdcfg[4], brdcfg4);
242 static int lx2160a_qds_mdio_read(struct mii_dev *bus, int addr,
243 int devad, int regnum)
245 struct lx2160a_qds_mdio *priv = bus->priv;
247 lx2160a_qds_mux_mdio(priv);
249 return priv->realbus->read(priv->realbus, addr, devad, regnum);
252 static int lx2160a_qds_mdio_write(struct mii_dev *bus, int addr, int devad,
253 int regnum, u16 value)
255 struct lx2160a_qds_mdio *priv = bus->priv;
257 lx2160a_qds_mux_mdio(priv);
259 return priv->realbus->write(priv->realbus, addr, devad, regnum, value);
262 static int lx2160a_qds_mdio_reset(struct mii_dev *bus)
264 struct lx2160a_qds_mdio *priv = bus->priv;
266 return priv->realbus->reset(priv->realbus);
269 static struct mii_dev *lx2160a_qds_mdio_init(u8 realbusnum, enum io_slot ioslot)
271 struct lx2160a_qds_mdio *pmdio;
273 /*should be within MDIO_NAME_LEN*/
274 char dummy_mdio_name[] = "LX2160A_QDS_MDIO1_IOSLOT1";
276 if (realbusnum == EMI2) {
277 if (ioslot < IO_SLOT_1 || ioslot > IO_SLOT_8) {
278 printf("invalid ioslot %d\n", ioslot);
281 } else if (realbusnum == EMI1) {
282 if (ioslot < IO_SLOT_1 || ioslot > EMI1_RGMII2) {
283 printf("invalid ioslot %d\n", ioslot);
287 printf("not supported real mdio bus %d\n", realbusnum);
291 if (ioslot == EMI1_RGMII1)
292 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII1");
293 else if (ioslot == EMI1_RGMII2)
294 strcpy(dummy_mdio_name, "LX2160A_QDS_MDIO1_RGMII2");
296 sprintf(dummy_mdio_name, "LX2160A_QDS_MDIO%d_IOSLOT%d",
298 bus = miiphy_get_dev_by_name(dummy_mdio_name);
305 printf("Failed to allocate %s bus\n", dummy_mdio_name);
309 pmdio = malloc(sizeof(*pmdio));
311 printf("Failed to allocate %s private data\n", dummy_mdio_name);
316 switch (realbusnum) {
319 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
323 miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
327 if (!pmdio->realbus) {
328 printf("No real mdio bus num %d found\n", realbusnum);
334 pmdio->realbusnum = realbusnum;
335 pmdio->ioslot = ioslot;
336 bus->read = lx2160a_qds_mdio_read;
337 bus->write = lx2160a_qds_mdio_write;
338 bus->reset = lx2160a_qds_mdio_reset;
339 strcpy(bus->name, dummy_mdio_name);
342 if (!mdio_register(bus))
345 printf("No bus with name %s\n", dummy_mdio_name);
351 static inline void do_phy_config(const struct phy_config *phy_config)
354 int i, phy_num, phy_address;
356 for (i = 0; i < SRDS_MAX_LANES; i++) {
357 if (!phy_config[i].dpmacid)
361 phy_num < ARRAY_SIZE(phy_config[i].phy_address);
363 phy_address = phy_config[i].phy_address[phy_num];
364 if (phy_address == -1)
366 wriop_set_phy_address(phy_config[i].dpmacid,
367 phy_num, phy_address);
369 /*Register the muxing front-ends to the MDIO buses*/
370 bus = lx2160a_qds_mdio_init(phy_config[i].mdio_bus,
371 phy_config[i].ioslot);
373 printf("could not get bus for mdio %d ioslot %d\n",
374 phy_config[i].mdio_bus,
375 phy_config[i].ioslot);
377 wriop_set_mdio(phy_config[i].dpmacid, bus);
381 static inline void do_dpmac_config(int dpmac, const char *arg_dpmacid,
386 u8 realbusnum, ioslot;
389 char *phystr = "phy00";
391 /*search phy in dpmac arg*/
392 for (phy_num = 0; phy_num < WRIOP_MAX_PHY_NUM; phy_num++) {
393 sprintf(phystr, "phy%d", phy_num + 1);
394 ret = hwconfig_subarg_f(arg_dpmacid, phystr, &len, env_dpmac);
396 /*look for phy instead of phy1*/
398 ret = hwconfig_subarg_f(arg_dpmacid, "phy",
404 if (len != 4 || strncmp(ret, "0x", 2))
405 printf("invalid phy format in %s variable.\n"
406 "specify phy%d for %s in hex format e.g. 0x12\n",
407 env_dpmac, phy_num + 1, arg_dpmacid);
409 wriop_set_phy_address(dpmac, phy_num,
410 simple_strtoul(ret, NULL, 16));
413 /*search mdio in dpmac arg*/
414 ret = hwconfig_subarg_f(arg_dpmacid, "mdio", &len, env_dpmac);
416 realbusnum = *ret - '0';
418 realbusnum = EMI_NONE;
421 /*search io in dpmac arg*/
422 ret = hwconfig_subarg_f(arg_dpmacid, "io", &len, env_dpmac);
426 ioslot = IO_SLOT_NONE;
427 /*Register the muxing front-ends to the MDIO buses*/
428 bus = lx2160a_qds_mdio_init(realbusnum, ioslot);
430 printf("could not get bus for mdio %d ioslot %d\n",
433 wriop_set_mdio(dpmac, bus);
439 int board_eth_init(bd_t *bis)
441 #if defined(CONFIG_FSL_MC_ENET)
442 struct memac_mdio_info mdio_info;
443 struct memac_mdio_controller *regs;
447 char dpmacid[] = "dpmac00", srds[] = "00_00_00";
450 const struct phy_config *phy_config;
451 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
452 u32 srds_s1, srds_s2, srds_s3;
454 srds_s1 = in_le32(&gur->rcwsr[28]) &
455 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
456 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
458 srds_s2 = in_le32(&gur->rcwsr[28]) &
459 FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_MASK;
460 srds_s2 >>= FSL_CHASSIS3_RCWSR28_SRDS2_PRTCL_SHIFT;
462 srds_s3 = in_le32(&gur->rcwsr[28]) &
463 FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_MASK;
464 srds_s3 >>= FSL_CHASSIS3_RCWSR28_SRDS3_PRTCL_SHIFT;
466 sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
468 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
469 mdio_info.regs = regs;
470 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
472 /*Register the EMI 1*/
473 fm_memac_mdio_init(bis, &mdio_info);
475 regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
476 mdio_info.regs = regs;
477 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
479 /*Register the EMI 2*/
480 fm_memac_mdio_init(bis, &mdio_info);
482 /* "dpmac" environment variable can be used after
483 * defining "dpmac_override" in hwconfig environment variable.
485 if (hwconfig("dpmac_override")) {
486 env_dpmac = env_get("dpmac");
488 ret = hwconfig_arg_f("srds", &len, env_dpmac);
490 if (strncmp(ret, srds, strlen(srds))) {
491 printf("SERDES configuration changed.\n"
492 "previous: %.*s, current: %s.\n"
493 "update dpmac variable.\n",
494 (int)len, ret, srds);
497 printf("SERDES configuration not found.\n"
498 "Please add srds:%s in dpmac variable\n",
502 for (i = WRIOP1_DPMAC1; i < NUM_WRIOP_PORTS; i++) {
503 /* Look for dpmac1 to dpmac24(current max) arg
504 * in dpmac environment variable
506 sprintf(dpmacid, "dpmac%d", i);
507 ret = hwconfig_arg_f(dpmacid, &len, env_dpmac);
509 do_dpmac_config(i, dpmacid, env_dpmac);
512 printf("Warning: environment dpmac not found.\n"
513 "DPAA network interfaces may not work\n");
516 /*Look for phy config for serdes1 in phy config table*/
517 phy_config = get_phy_config(srds_s1, serdes1_phy_config,
518 ARRAY_SIZE(serdes1_phy_config));
520 printf("%s WRIOP: Unsupported SerDes1 Protocol %d\n",
523 do_phy_config(phy_config);
525 phy_config = get_phy_config(srds_s2, serdes2_phy_config,
526 ARRAY_SIZE(serdes2_phy_config));
528 printf("%s WRIOP: Unsupported SerDes2 Protocol %d\n",
531 do_phy_config(phy_config);
533 phy_config = get_phy_config(srds_s3, serdes3_phy_config,
534 ARRAY_SIZE(serdes3_phy_config));
536 printf("%s WRIOP: Unsupported SerDes3 Protocol %d\n",
539 do_phy_config(phy_config);
543 if (wriop_get_enet_if(WRIOP1_DPMAC17) == PHY_INTERFACE_MODE_RGMII_ID) {
544 wriop_set_phy_address(WRIOP1_DPMAC17, 0, RGMII_PHY_ADDR1);
545 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII1);
547 printf("could not get bus for RGMII1\n");
549 wriop_set_mdio(WRIOP1_DPMAC17, bus);
552 if (wriop_get_enet_if(WRIOP1_DPMAC18) == PHY_INTERFACE_MODE_RGMII_ID) {
553 wriop_set_phy_address(WRIOP1_DPMAC18, 0, RGMII_PHY_ADDR2);
554 bus = lx2160a_qds_mdio_init(EMI1, EMI1_RGMII2);
556 printf("could not get bus for RGMII2\n");
558 wriop_set_mdio(WRIOP1_DPMAC18, bus);
562 #endif /* CONFIG_FMAN_ENET */
564 #ifdef CONFIG_PHY_AQUANTIA
566 * Export functions to be used by AQ firmware
569 gd->jt->strcpy = strcpy;
570 gd->jt->mdelay = mdelay;
571 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
572 gd->jt->phy_find_by_mask = phy_find_by_mask;
573 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
574 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
576 return pci_eth_init(bis);
579 #if defined(CONFIG_RESET_PHY_R)
582 #if defined(CONFIG_FSL_MC_ENET)
586 #endif /* CONFIG_RESET_PHY_R */
588 #if defined(CONFIG_FSL_MC_ENET)
589 int fdt_fixup_dpmac_phy_handle(void *fdt, int dpmac_id, int node_phandle)
593 char dpmac_str[] = "dpmacs@00";
594 const char *phy_string;
596 offset = fdt_path_offset(fdt, "/soc/fsl-mc/dpmacs");
599 offset = fdt_path_offset(fdt, "/fsl-mc/dpmacs");
602 printf("dpmacs node not found in device tree\n");
606 sprintf(dpmac_str, "dpmac@%x", dpmac_id);
607 debug("dpmac_str = %s\n", dpmac_str);
609 offset = fdt_subnode_offset(fdt, offset, dpmac_str);
611 printf("%s node not found in device tree\n", dpmac_str);
615 ret = fdt_appendprop_cell(fdt, offset, "phy-handle", node_phandle);
617 printf("%d@%s %d\n", __LINE__, __func__, ret);
619 phy_string = phy_string_for_interface(wriop_get_enet_if(dpmac_id));
620 ret = fdt_setprop_string(fdt, offset, "phy-connection-type",
623 printf("%d@%s %d\n", __LINE__, __func__, ret);
628 int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset)
630 char mdio_ioslot_str[] = "mdio@00";
631 char mdio_mux_str[] = "mdio-mux-0";
632 struct lx2160a_qds_mdio *priv;
635 /*Test if the MDIO bus is real mdio bus or muxing front end ?*/
636 if (strncmp(mii_dev->name, "LX2160A_QDS_MDIO",
637 strlen("LX2160A_QDS_MDIO")))
640 /*Get the real MDIO bus num and ioslot info from bus's priv data*/
641 priv = mii_dev->priv;
643 debug("real_bus_num = %d, ioslot = %d\n",
644 priv->realbusnum, priv->ioslot);
646 sprintf(mdio_mux_str, "mdio-mux-%1d", priv->realbusnum);
647 offset = fdt_subnode_offset(fdt, fpga_offset, mdio_mux_str);
649 printf("%s node not found under node %s in device tree\n",
650 mdio_mux_str, fdt_get_name(fdt, fpga_offset, NULL));
654 mux_val = lx2160a_qds_get_mdio_mux_val(priv->realbusnum, priv->ioslot);
655 sprintf(mdio_ioslot_str, "mdio@%x", (u8)mux_val);
657 offset = fdt_subnode_offset(fdt, offset, mdio_ioslot_str);
659 printf("%s node not found in device tree\n", mdio_ioslot_str);
666 int fdt_create_phy_node(void *fdt, int offset, u8 phyaddr, int *subnodeoffset,
667 struct phy_device *phy_dev, int phandle)
669 char phy_node_name[] = "ethernet-phy@00";
670 char phy_id_compatible_str[] = "ethernet-phy-id0000.0000";
673 sprintf(phy_node_name, "ethernet-phy@%x", phyaddr);
674 debug("phy_node_name = %s\n", phy_node_name);
676 *subnodeoffset = fdt_add_subnode(fdt, offset, phy_node_name);
677 if (*subnodeoffset <= 0) {
678 printf("Could not add subnode %s\n", phy_node_name);
679 return *subnodeoffset;
682 sprintf(phy_id_compatible_str, "ethernet-phy-id%04x.%04x",
683 phy_dev->phy_id >> 16, phy_dev->phy_id & 0xFFFF);
684 debug("phy_id_compatible_str %s\n", phy_id_compatible_str);
686 ret = fdt_setprop_string(fdt, *subnodeoffset, "compatible",
687 phy_id_compatible_str);
689 printf("%d@%s %d\n", __LINE__, __func__, ret);
693 if (phy_dev->is_c45) {
694 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
695 "ethernet-phy-ieee802.3-c45");
697 printf("%d@%s %d\n", __LINE__, __func__, ret);
701 ret = fdt_appendprop_string(fdt, *subnodeoffset, "compatible",
702 "ethernet-phy-ieee802.3-c22");
704 printf("%d@%s %d\n", __LINE__, __func__, ret);
709 ret = fdt_setprop_cell(fdt, *subnodeoffset, "reg", phyaddr);
711 printf("%d@%s %d\n", __LINE__, __func__, ret);
715 ret = fdt_set_phandle(fdt, *subnodeoffset, phandle);
717 printf("%d@%s %d\n", __LINE__, __func__, ret);
723 fdt_del_node(fdt, *subnodeoffset);
728 int fdt_fixup_board_phy(void *fdt)
730 int fpga_offset, offset, subnodeoffset;
731 struct mii_dev *mii_dev;
732 struct list_head *mii_devs, *entry;
733 int ret, dpmac_id, phandle, i;
734 struct phy_device *phy_dev;
735 char ethname[ETH_NAME_LEN];
736 phy_interface_t phy_iface;
739 /* we know FPGA is connected to i2c0, therefore search path directly,
740 * instead of compatible property, as it saves time
742 fpga_offset = fdt_path_offset(fdt, "/soc/i2c@2000000/fpga");
745 fpga_offset = fdt_path_offset(fdt, "/i2c@2000000/fpga");
747 if (fpga_offset < 0) {
748 printf("i2c@2000000/fpga node not found in device tree\n");
752 phandle = fdt_alloc_phandle(fdt);
753 mii_devs = mdio_get_list_head();
755 list_for_each(entry, mii_devs) {
756 mii_dev = list_entry(entry, struct mii_dev, link);
757 debug("mii_dev name : %s\n", mii_dev->name);
758 offset = fdt_get_ioslot_offset(fdt, mii_dev, fpga_offset);
762 // Look for phy devices attached to MDIO bus muxing front end
763 // and create their entries with compatible being the device id
764 for (i = 0; i < PHY_MAX_ADDR; i++) {
765 phy_dev = mii_dev->phymap[i];
769 // TODO: use sscanf instead of loop
770 dpmac_id = WRIOP1_DPMAC1;
771 while (dpmac_id < NUM_WRIOP_PORTS) {
772 phy_iface = wriop_get_enet_if(dpmac_id);
773 snprintf(ethname, ETH_NAME_LEN, "DPMAC%d@%s",
775 phy_string_for_interface(phy_iface));
776 if (strcmp(ethname, phy_dev->dev->name) == 0)
780 if (dpmac_id == NUM_WRIOP_PORTS)
783 ret = fdt_create_phy_node(fdt, offset, i,
789 ret = fdt_fixup_dpmac_phy_handle(fdt,
792 fdt_del_node(fdt, subnodeoffset);
804 #endif // CONFIG_FSL_MC_ENET