2 * Copyright 2015 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/fsl_serdes.h>
19 #include <asm/arch-fsl-lsch3/immap_lsch3.h>
20 #include <fsl-mc/ldpaa_wriop.h>
22 DECLARE_GLOBAL_DATA_PTR;
24 int load_firmware_cortina(struct phy_device *phy_dev)
26 if (phy_dev->drv->config)
27 return phy_dev->drv->config(phy_dev);
32 void load_phy_firmware(void)
36 struct phy_device *phy_dev;
38 phy_interface_t interface;
40 /*Initialize and upload firmware for all the PHYs*/
41 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
42 interface = wriop_get_enet_if(i);
43 if (interface == PHY_INTERFACE_MODE_XGMII) {
44 dev = wriop_get_mdio(i);
45 phy_addr = wriop_get_phy_address(i);
46 phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
49 printf("No phydev for phyaddr %d\n", phy_addr);
53 /*Flash firmware for All CS4340 PHYS */
54 if (phy_dev->phy_id == PHY_UID_CS4340)
55 load_firmware_cortina(phy_dev);
60 int board_eth_init(bd_t *bis)
62 #if defined(CONFIG_FSL_MC_ENET)
64 struct memac_mdio_info mdio_info;
66 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
68 struct memac_mdio_controller *reg;
70 srds_s1 = in_le32(&gur->rcwsr[28]) &
71 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
72 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
74 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
76 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
78 /* Register the EMI 1 */
79 fm_memac_mdio_init(bis, &mdio_info);
81 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
83 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
85 /* Register the EMI 2 */
86 fm_memac_mdio_init(bis, &mdio_info);
90 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
91 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
92 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
93 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
94 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
95 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
96 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
97 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
101 printf("SerDes1 protocol 0x%x is not supported on LS2085aRDB\n",
106 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
107 interface = wriop_get_enet_if(i);
109 case PHY_INTERFACE_MODE_XGMII:
110 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
111 wriop_set_mdio(i, dev);
118 for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
119 switch (wriop_get_enet_if(i)) {
120 case PHY_INTERFACE_MODE_XGMII:
121 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
122 wriop_set_mdio(i, dev);
129 /* Load CORTINA CS4340 PHY firmware */
133 #endif /* CONFIG_FMAN_ENET */
135 #ifdef CONFIG_PHY_AQUANTIA
137 * Export functions to be used by AQ firmware
140 gd->jt->strcpy = strcpy;
141 gd->jt->mdelay = mdelay;
142 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
143 gd->jt->phy_find_by_mask = phy_find_by_mask;
144 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
145 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
147 return pci_eth_init(bis);