2 * Copyright 2015 Freescale Semiconductor, Inc.
5 * SPDX-License-Identifier: GPL-2.0+
18 #include <asm/arch/fsl_serdes.h>
19 #include <fsl-mc/ldpaa_wriop.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 int load_firmware_cortina(struct phy_device *phy_dev)
25 if (phy_dev->drv->config)
26 return phy_dev->drv->config(phy_dev);
31 void load_phy_firmware(void)
35 struct phy_device *phy_dev;
37 phy_interface_t interface;
39 /*Initialize and upload firmware for all the PHYs*/
40 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC8; i++) {
41 interface = wriop_get_enet_if(i);
42 if (interface == PHY_INTERFACE_MODE_XGMII) {
43 dev = wriop_get_mdio(i);
44 phy_addr = wriop_get_phy_address(i);
45 phy_dev = phy_find_by_mask(dev, 1 << phy_addr,
48 printf("No phydev for phyaddr %d\n", phy_addr);
52 /*Flash firmware for All CS4340 PHYS */
53 if (phy_dev->phy_id == PHY_UID_CS4340)
54 load_firmware_cortina(phy_dev);
59 int board_eth_init(bd_t *bis)
61 #if defined(CONFIG_FSL_MC_ENET)
63 struct memac_mdio_info mdio_info;
65 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
67 struct memac_mdio_controller *reg;
69 srds_s1 = in_le32(&gur->rcwsr[28]) &
70 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
71 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
73 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
75 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
77 /* Register the EMI 1 */
78 fm_memac_mdio_init(bis, &mdio_info);
80 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
82 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
84 /* Register the EMI 2 */
85 fm_memac_mdio_init(bis, &mdio_info);
89 wriop_set_phy_address(WRIOP1_DPMAC1, CORTINA_PHY_ADDR1);
90 wriop_set_phy_address(WRIOP1_DPMAC2, CORTINA_PHY_ADDR2);
91 wriop_set_phy_address(WRIOP1_DPMAC3, CORTINA_PHY_ADDR3);
92 wriop_set_phy_address(WRIOP1_DPMAC4, CORTINA_PHY_ADDR4);
93 wriop_set_phy_address(WRIOP1_DPMAC5, AQ_PHY_ADDR1);
94 wriop_set_phy_address(WRIOP1_DPMAC6, AQ_PHY_ADDR2);
95 wriop_set_phy_address(WRIOP1_DPMAC7, AQ_PHY_ADDR3);
96 wriop_set_phy_address(WRIOP1_DPMAC8, AQ_PHY_ADDR4);
100 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
105 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
106 interface = wriop_get_enet_if(i);
108 case PHY_INTERFACE_MODE_XGMII:
109 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
110 wriop_set_mdio(i, dev);
117 for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
118 switch (wriop_get_enet_if(i)) {
119 case PHY_INTERFACE_MODE_XGMII:
120 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
121 wriop_set_mdio(i, dev);
128 /* Load CORTINA CS4340 PHY firmware */
132 #endif /* CONFIG_FMAN_ENET */
134 #ifdef CONFIG_PHY_AQUANTIA
136 * Export functions to be used by AQ firmware
139 gd->jt->strcpy = strcpy;
140 gd->jt->mdelay = mdelay;
141 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
142 gd->jt->phy_find_by_mask = phy_find_by_mask;
143 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
144 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
146 return pci_eth_init(bis);