1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
17 #include <asm/arch/fsl_serdes.h>
18 #include <fsl-mc/fsl_mc.h>
19 #include <fsl-mc/ldpaa_wriop.h>
21 DECLARE_GLOBAL_DATA_PTR;
23 int board_eth_init(bd_t *bis)
25 #if defined(CONFIG_FSL_MC_ENET)
27 struct memac_mdio_info mdio_info;
29 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
31 struct memac_mdio_controller *reg;
33 srds_s1 = in_le32(&gur->rcwsr[28]) &
34 FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK;
35 srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
37 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1;
39 mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
41 /* Register the EMI 1 */
42 fm_memac_mdio_init(bis, &mdio_info);
44 reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2;
46 mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
48 /* Register the EMI 2 */
49 fm_memac_mdio_init(bis, &mdio_info);
53 wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
54 wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
55 wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
56 wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
57 wriop_set_phy_address(WRIOP1_DPMAC5, 0, AQ_PHY_ADDR1);
58 wriop_set_phy_address(WRIOP1_DPMAC6, 0, AQ_PHY_ADDR2);
59 wriop_set_phy_address(WRIOP1_DPMAC7, 0, AQ_PHY_ADDR3);
60 wriop_set_phy_address(WRIOP1_DPMAC8, 0, AQ_PHY_ADDR4);
64 wriop_set_phy_address(WRIOP1_DPMAC1, 0, CORTINA_PHY_ADDR1);
65 wriop_set_phy_address(WRIOP1_DPMAC2, 0, CORTINA_PHY_ADDR2);
66 wriop_set_phy_address(WRIOP1_DPMAC3, 0, CORTINA_PHY_ADDR3);
67 wriop_set_phy_address(WRIOP1_DPMAC4, 0, CORTINA_PHY_ADDR4);
71 printf("SerDes1 protocol 0x%x is not supported on LS2080aRDB\n",
76 for (i = WRIOP1_DPMAC1; i <= WRIOP1_DPMAC4; i++) {
77 interface = wriop_get_enet_if(i);
79 case PHY_INTERFACE_MODE_XGMII:
80 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO1_NAME);
81 wriop_set_mdio(i, dev);
88 for (i = WRIOP1_DPMAC5; i <= WRIOP1_DPMAC8; i++) {
89 switch (wriop_get_enet_if(i)) {
90 case PHY_INTERFACE_MODE_XGMII:
91 dev = miiphy_get_dev_by_name(DEFAULT_WRIOP_MDIO2_NAME);
92 wriop_set_mdio(i, dev);
100 #endif /* CONFIG_FSL_MC_ENET */
102 #ifdef CONFIG_PHY_AQUANTIA
104 * Export functions to be used by AQ firmware
107 gd->jt->strcpy = strcpy;
108 gd->jt->mdelay = mdelay;
109 gd->jt->mdio_get_current_dev = mdio_get_current_dev;
110 gd->jt->phy_find_by_mask = phy_find_by_mask;
111 gd->jt->mdio_phydev_for_ethname = mdio_phydev_for_ethname;
112 gd->jt->miiphy_set_current_dev = miiphy_set_current_dev;
114 return pci_eth_init(bis);
117 #if defined(CONFIG_RESET_PHY_R)
122 #endif /* CONFIG_RESET_PHY_R */