1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor
13 #include <fdt_support.h>
14 #include <linux/libfdt.h>
15 #include <fsl-mc/fsl_mc.h>
16 #include <env_internal.h>
19 #include <asm/arch/soc.h>
22 #include <asm/arch/ppa.h>
23 #include <asm/arch-fsl-layerscape/fsl_icid.h>
26 #include "../common/qixis.h"
27 #include "ls2080aqds_qixis.h"
28 #include "../common/vid.h"
30 #define PIN_MUX_SEL_SDHC 0x00
31 #define PIN_MUX_SEL_DSPI 0x0a
32 #define SCFG_QSPICLKCTRL_DIV_20 (5 << 27)
34 #define SET_SDHC_MUX_SEL(reg, value) ((reg & 0xf0) | value)
36 DECLARE_GLOBAL_DATA_PTR;
43 unsigned long long get_qixis_addr(void)
45 unsigned long long addr;
47 if (gd->flags & GD_FLG_RELOC)
48 addr = QIXIS_BASE_PHYS;
50 addr = QIXIS_BASE_PHYS_EARLY;
53 * IFC address under 256MB is mapped to 0x30000000, any address above
54 * is mapped to 0x5_10000000 up to 4GB.
56 addr = addr > 0x10000000 ? addr + 0x500000000ULL : addr + 0x30000000;
65 static const char *const freq[] = {"100", "125", "156.25",
70 printf("Board: %s-QDS, ", buf);
72 sw = QIXIS_READ(arch);
73 printf("Board Arch: V%d, ", sw >> 4);
74 printf("Board version: %c, boot from ", (sw & 0xf) + 'A' - 1);
76 memset((u8 *)buf, 0x00, ARRAY_SIZE(buf));
78 sw = QIXIS_READ(brdcfg[0]);
79 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
82 printf("vBank: %d\n", sw);
92 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
94 printf("FPGA: v%d (%s), build %d",
95 (int)QIXIS_READ(scver), qixis_read_tag(buf),
96 (int)qixis_read_minor());
97 /* the timestamp string contains "\n" at the end */
98 printf(" on %s", qixis_read_time(buf));
101 * Display the actual SERDES reference clocks as configured by the
102 * dip switches on the board. Note that the SWx registers could
103 * technically be set to force the reference clocks to match the
104 * values that the SERDES expects (or vice versa). For now, however,
105 * we just display both values and hope the user notices when they
108 puts("SERDES1 Reference : ");
109 sw = QIXIS_READ(brdcfg[2]);
110 clock = (sw >> 6) & 3;
111 printf("Clock1 = %sMHz ", freq[clock]);
112 clock = (sw >> 4) & 3;
113 printf("Clock2 = %sMHz", freq[clock]);
115 puts("\nSERDES2 Reference : ");
116 clock = (sw >> 2) & 3;
117 printf("Clock1 = %sMHz ", freq[clock]);
118 clock = (sw >> 0) & 3;
119 printf("Clock2 = %sMHz\n", freq[clock]);
124 unsigned long get_board_sys_clk(void)
126 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
128 switch (sysclk_conf & 0x0F) {
129 case QIXIS_SYSCLK_83:
131 case QIXIS_SYSCLK_100:
133 case QIXIS_SYSCLK_125:
135 case QIXIS_SYSCLK_133:
137 case QIXIS_SYSCLK_150:
139 case QIXIS_SYSCLK_160:
141 case QIXIS_SYSCLK_166:
147 unsigned long get_board_ddr_clk(void)
149 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
151 switch ((ddrclk_conf & 0x30) >> 4) {
152 case QIXIS_DDRCLK_100:
154 case QIXIS_DDRCLK_125:
156 case QIXIS_DDRCLK_133:
162 int select_i2c_ch_pca9547(u8 ch)
168 ret = i2c_get_chip_for_busnum(0, I2C_MUX_PCA_ADDR_PRI, 1, &dev);
170 ret = dm_i2c_write(dev, 0, &ch, 1);
173 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
176 puts("PCA: failed to select proper channel\n");
183 int config_board_mux(int ctrl_type)
187 reg5 = QIXIS_READ(brdcfg[5]);
191 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_SDHC);
194 reg5 = SET_SDHC_MUX_SEL(reg5, PIN_MUX_SEL_DSPI);
197 printf("Wrong mux interface type\n");
201 QIXIS_WRITE(brdcfg[5], reg5);
209 u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE;
212 init_final_memctl_regs();
214 val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4);
216 env_hwconfig = env_get("hwconfig");
218 if (hwconfig_f("dspi", env_hwconfig) &&
219 DCFG_RCWSR13_DSPI == (val & (u32)(0xf << 8)))
220 config_board_mux(MUX_TYPE_DSPI);
222 config_board_mux(MUX_TYPE_SDHC);
224 #if defined(CONFIG_MTD_RAW_NAND) && defined(CONFIG_FSL_QSPI)
225 val = in_le32(dcfg_ccsr + DCFG_RCWSR15 / 4);
227 if (DCFG_RCWSR15_IFCGRPABASE_QSPI == (val & (u32)0x3))
228 QIXIS_WRITE(brdcfg[9],
229 (QIXIS_READ(brdcfg[9]) & 0xf8) |
230 FSL_QIXIS_BRDCFG9_QSPI);
233 #ifdef CONFIG_ENV_IS_NOWHERE
234 gd->env_addr = (ulong)&default_environment[0];
236 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
238 #ifdef CONFIG_RTC_ENABLE_32KHZ_OUTPUT
240 rtc_enable_32khz_output(0, CONFIG_SYS_I2C_RTC_ADDR);
242 rtc_enable_32khz_output();
246 #ifdef CONFIG_FSL_CAAM
250 #ifdef CONFIG_FSL_LS_PPA
254 #if !defined(CONFIG_SYS_EARLY_PCI_INIT) && defined(CONFIG_DM_ETH)
261 int board_early_init_f(void)
263 #ifdef CONFIG_SYS_I2C_EARLY_INIT
266 fsl_lsch3_early_init_f();
267 #ifdef CONFIG_FSL_QSPI
268 /* input clk: 1/2 platform clk, output: input/20 */
269 out_le32(SCFG_BASE + SCFG_QSPICLKCTLR, SCFG_QSPICLKCTRL_DIV_20);
274 int misc_init_r(void)
277 printf("Warning: Adjusting core voltage failed.\n");
282 void detail_board_ddr_info(void)
285 print_size(gd->bd->bi_dram[0].size + gd->bd->bi_dram[1].size, "");
287 #ifdef CONFIG_SYS_FSL_HAS_DP_DDR
288 if (soc_has_dp_ddr() && gd->bd->bi_dram[2].size) {
290 print_size(gd->bd->bi_dram[2].size, "");
291 print_ddr_info(CONFIG_DP_DDR_CTRL);
296 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
297 void fdt_fixup_board_enet(void *fdt)
301 offset = fdt_path_offset(fdt, "/soc/fsl-mc");
304 offset = fdt_path_offset(fdt, "/fsl-mc");
307 printf("%s: ERROR: fsl-mc node not found in device tree (error %d)\n",
312 if (get_mc_boot_status() == 0 &&
313 (is_lazy_dpl_addr_valid() || get_dpl_apply_status() == 0))
314 fdt_status_okay(fdt, offset);
316 fdt_status_fail(fdt, offset);
319 void board_quiesce_devices(void)
321 fsl_mc_ldpaa_exit(gd->bd);
325 #ifdef CONFIG_OF_BOARD_SETUP
326 int ft_board_setup(void *blob, bd_t *bd)
328 u64 base[CONFIG_NR_DRAM_BANKS];
329 u64 size[CONFIG_NR_DRAM_BANKS];
331 ft_cpu_setup(blob, bd);
333 /* fixup DT for the two GPP DDR banks */
334 base[0] = gd->bd->bi_dram[0].start;
335 size[0] = gd->bd->bi_dram[0].size;
336 base[1] = gd->bd->bi_dram[1].start;
337 size[1] = gd->bd->bi_dram[1].size;
339 #ifdef CONFIG_RESV_RAM
340 /* reduce size if reserved memory is within this bank */
341 if (gd->arch.resv_ram >= base[0] &&
342 gd->arch.resv_ram < base[0] + size[0])
343 size[0] = gd->arch.resv_ram - base[0];
344 else if (gd->arch.resv_ram >= base[1] &&
345 gd->arch.resv_ram < base[1] + size[1])
346 size[1] = gd->arch.resv_ram - base[1];
349 fdt_fixup_memory_banks(blob, base, size, 2);
351 fdt_fsl_mc_fixup_iommu_map_entry(blob);
353 fsl_fdt_fixup_dr_usb(blob, bd);
355 #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD)
356 fdt_fixup_board_enet(blob);
359 fdt_fixup_icid(blob);
365 void qixis_dump_switch(void)
369 QIXIS_WRITE(cms[0], 0x00);
370 nr_of_cfgsw = QIXIS_READ(cms[1]);
372 puts("DIP switch settings dump:\n");
373 for (i = 1; i <= nr_of_cfgsw; i++) {
374 QIXIS_WRITE(cms[0], i);
375 printf("SW%d = (0x%02x)\n", i, QIXIS_READ(cms[1]));