board/freescale/ls1046ardb/ddr.c

   1 // SPDX-License-Identifier: GPL-2.0+
   2 /*
   3  * Copyright 2016 Freescale Semiconductor, Inc.
   4  */
   5
   6 #include <common.h>
   7 #include <fsl_ddr_sdram.h>
   8 #include <fsl_ddr_dimm_params.h>
   9 #include "ddr.h"
  10 #ifdef CONFIG_FSL_DEEP_SLEEP
  11 #include <fsl_sleep.h>
  12 #endif
  13 #include <asm/arch/clock.h>
  14
  15 DECLARE_GLOBAL_DATA_PTR;
  16
  17 void fsl_ddr_board_options(memctl_options_t *popts,
  18                            dimm_params_t *pdimm,
  19                            unsigned int ctrl_num)
  20 {
  21         const struct board_specific_parameters *pbsp, *pbsp_highest = NULL;
  22         ulong ddr_freq;
  23
  24         if (ctrl_num > 1) {
  25                 printf("Not supported controller number %d\n", ctrl_num);
  26                 return;
  27         }
  28         if (!pdimm->n_ranks)
  29                 return;
  30
  31         if (popts->registered_dimm_en)
  32                 pbsp = rdimms[0];
  33         else
  34                 pbsp = udimms[0];
  35
  36         /* Get clk_adjust, wrlvl_start, wrlvl_ctl, according to the board ddr
  37          * freqency and n_banks specified in board_specific_parameters table.
  38          */
  39         ddr_freq = get_ddr_freq(0) / 1000000;
  40         while (pbsp->datarate_mhz_high) {
  41                 if (pbsp->n_ranks == pdimm->n_ranks) {
  42                         if (ddr_freq <= pbsp->datarate_mhz_high) {
  43                                 popts->clk_adjust = pbsp->clk_adjust;
  44                                 popts->wrlvl_start = pbsp->wrlvl_start;
  45                                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  46                                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  47                                 goto found;
  48                         }
  49                         pbsp_highest = pbsp;
  50                 }
  51                 pbsp++;
  52         }
  53
  54         if (pbsp_highest) {
  55                 printf("Error: board specific timing not found for %lu MT/s\n",
  56                        ddr_freq);
  57                 printf("Trying to use the highest speed (%u) parameters\n",
  58                        pbsp_highest->datarate_mhz_high);
  59                 popts->clk_adjust = pbsp_highest->clk_adjust;
  60                 popts->wrlvl_start = pbsp_highest->wrlvl_start;
  61                 popts->wrlvl_ctl_2 = pbsp->wrlvl_ctl_2;
  62                 popts->wrlvl_ctl_3 = pbsp->wrlvl_ctl_3;
  63         } else {
  64                 panic("DIMM is not supported by this board");
  65         }
  66 found:
  67         debug("Found timing match: n_ranks %d, data rate %d, rank_gb %d\n",
  68               pbsp->n_ranks, pbsp->datarate_mhz_high, pbsp->rank_gb);
  69
  70         popts->data_bus_width = 0;      /* 64-bit data bus */
  71         popts->bstopre = 0;             /* enable auto precharge */
  72
  73         /*
  74          * Factors to consider for half-strength driver enable:
  75          *      - number of DIMMs installed
  76          */
  77         popts->half_strength_driver_enable = 0;
  78         /*
  79          * Write leveling override
  80          */
  81         popts->wrlvl_override = 1;
  82         popts->wrlvl_sample = 0xf;
  83
  84         /*
  85          * Rtt and Rtt_WR override
  86          */
  87         popts->rtt_override = 0;
  88
  89         /* Enable ZQ calibration */
  90         popts->zq_en = 1;
  91
  92         popts->ddr_cdr1 = DDR_CDR1_DHC_EN | DDR_CDR1_ODT(DDR_CDR_ODT_80ohm);
  93         popts->ddr_cdr2 = DDR_CDR2_ODT(DDR_CDR_ODT_80ohm) |
  94                           DDR_CDR2_VREF_TRAIN_EN | DDR_CDR2_VREF_RANGE_2;
  95
  96         /* optimize cpo for erratum A-009942 */
  97         popts->cpo_sample = 0x61;
  98 }
  99
 100 #ifdef CONFIG_TFABOOT
 101 int fsl_initdram(void)
 102 {
 103         gd->ram_size = tfa_get_dram_size();
 104
 105         if (!gd->ram_size)
 106                 gd->ram_size = fsl_ddr_sdram_size();
 107
 108         return 0;
 109 }
 110 #else
 111 int fsl_initdram(void)
 112 {
 113         phys_size_t dram_size;
 114
 115 #if defined(CONFIG_SPL) && !defined(CONFIG_SPL_BUILD)
 116         gd->ram_size = fsl_ddr_sdram_size();
 117
 118         return 0;
 119 #else
 120         puts("Initializing DDR....using SPD\n");
 121
 122         dram_size = fsl_ddr_sdram();
 123 #endif
 124
 125         erratum_a008850_post();
 126
 127         gd->ram_size = dram_size;
 128
 129         return 0;
 130 }
 131 #endif