1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
8 #include <fdt_support.h>
9 #include <fsl_ddr_sdram.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/fsl_serdes.h>
13 #include <asm/arch/ppa.h>
14 #include <asm/arch/fdt.h>
15 #include <asm/arch/mmu.h>
16 #include <asm/arch/cpu.h>
17 #include <asm/arch/soc.h>
18 #include <asm/arch-fsl-layerscape/fsl_icid.h>
25 #include <fsl_esdhc.h>
30 #include "../common/vid.h"
31 #include "../common/qixis.h"
32 #include "ls1046aqds_qixis.h"
34 DECLARE_GLOBAL_DATA_PTR;
37 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
41 CONFIG_SYS_NOR0_CSPR_EXT,
55 CONFIG_SYS_NOR1_CSPR_EXT,
68 CONFIG_SYS_NAND_CSPR_EXT,
69 CONFIG_SYS_NAND_AMASK,
72 CONFIG_SYS_NAND_FTIM0,
73 CONFIG_SYS_NAND_FTIM1,
74 CONFIG_SYS_NAND_FTIM2,
81 CONFIG_SYS_FPGA_CSPR_EXT,
82 CONFIG_SYS_FPGA_AMASK,
85 CONFIG_SYS_FPGA_FTIM0,
86 CONFIG_SYS_FPGA_FTIM1,
87 CONFIG_SYS_FPGA_FTIM2,
93 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
97 CONFIG_SYS_NAND_CSPR_EXT,
98 CONFIG_SYS_NAND_AMASK,
101 CONFIG_SYS_NAND_FTIM0,
102 CONFIG_SYS_NAND_FTIM1,
103 CONFIG_SYS_NAND_FTIM2,
104 CONFIG_SYS_NAND_FTIM3
109 CONFIG_SYS_NOR0_CSPR,
110 CONFIG_SYS_NOR0_CSPR_EXT,
111 CONFIG_SYS_NOR_AMASK,
114 CONFIG_SYS_NOR_FTIM0,
115 CONFIG_SYS_NOR_FTIM1,
116 CONFIG_SYS_NOR_FTIM2,
122 CONFIG_SYS_NOR1_CSPR,
123 CONFIG_SYS_NOR1_CSPR_EXT,
124 CONFIG_SYS_NOR_AMASK,
127 CONFIG_SYS_NOR_FTIM0,
128 CONFIG_SYS_NOR_FTIM1,
129 CONFIG_SYS_NOR_FTIM2,
135 CONFIG_SYS_FPGA_CSPR,
136 CONFIG_SYS_FPGA_CSPR_EXT,
137 CONFIG_SYS_FPGA_AMASK,
138 CONFIG_SYS_FPGA_CSOR,
140 CONFIG_SYS_FPGA_FTIM0,
141 CONFIG_SYS_FPGA_FTIM1,
142 CONFIG_SYS_FPGA_FTIM2,
143 CONFIG_SYS_FPGA_FTIM3
148 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
150 enum boot_src src = get_boot_src();
152 if (src == BOOT_SOURCE_IFC_NAND)
153 regs_info->regs = ifc_cfg_nand_boot;
155 regs_info->regs = ifc_cfg_nor_boot;
156 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
167 #ifdef CONFIG_TFABOOT
168 enum boot_src src = get_boot_src();
171 #ifndef CONFIG_SD_BOOT
175 puts("Board: LS1046AQDS, boot from ");
177 #ifdef CONFIG_TFABOOT
178 if (src == BOOT_SOURCE_SD_MMC)
183 #ifdef CONFIG_SD_BOOT
186 sw = QIXIS_READ(brdcfg[0]);
187 sw = (sw & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
190 printf("vBank: %d\n", sw);
198 printf("invalid setting of SW%u\n", QIXIS_LBMAP_SWITCH);
201 #ifdef CONFIG_TFABOOT
204 printf("Sys ID: 0x%02x, Sys Ver: 0x%02x\n",
205 QIXIS_READ(id), QIXIS_READ(arch));
207 printf("FPGA: v%d (%s), build %d\n",
208 (int)QIXIS_READ(scver), qixis_read_tag(buf),
209 (int)qixis_read_minor());
214 bool if_board_diff_clk(void)
216 u8 diff_conf = QIXIS_READ(brdcfg[11]);
218 return diff_conf & 0x40;
221 unsigned long get_board_sys_clk(void)
223 u8 sysclk_conf = QIXIS_READ(brdcfg[1]);
225 switch (sysclk_conf & 0x0f) {
226 case QIXIS_SYSCLK_64:
228 case QIXIS_SYSCLK_83:
230 case QIXIS_SYSCLK_100:
232 case QIXIS_SYSCLK_125:
234 case QIXIS_SYSCLK_133:
236 case QIXIS_SYSCLK_150:
238 case QIXIS_SYSCLK_160:
240 case QIXIS_SYSCLK_166:
247 unsigned long get_board_ddr_clk(void)
249 u8 ddrclk_conf = QIXIS_READ(brdcfg[1]);
251 if (if_board_diff_clk())
252 return get_board_sys_clk();
253 switch ((ddrclk_conf & 0x30) >> 4) {
254 case QIXIS_DDRCLK_100:
256 case QIXIS_DDRCLK_125:
258 case QIXIS_DDRCLK_133:
266 u32 get_lpuart_clk(void)
272 int select_i2c_ch_pca9547(u8 ch)
276 ret = i2c_write(I2C_MUX_PCA_ADDR_PRI, 0, 1, &ch, 1);
278 puts("PCA: failed to select proper channel\n");
288 * When resuming from deep sleep, the I2C channel may not be
289 * in the default channel. So, switch to the default channel
290 * before accessing DDR SPD.
292 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
294 #if (!defined(CONFIG_SPL) && !defined(CONFIG_TFABOOT)) || \
295 defined(CONFIG_SPL_BUILD)
296 /* This will break-before-make MMU for DDR */
297 update_early_mmu_table();
303 int i2c_multiplexer_select_vid_channel(u8 channel)
305 return select_i2c_ch_pca9547(channel);
308 int board_early_init_f(void)
310 #ifdef CONFIG_HAS_FSL_XHCI_USB
311 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
318 #ifdef CONFIG_SYS_I2C_EARLY_INIT
321 fsl_lsch2_early_init_f();
323 #ifdef CONFIG_HAS_FSL_XHCI_USB
324 out_be32(&scfg->rcwpmuxcr0, 0x3333);
325 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
326 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
327 SCFG_USBPWRFAULT_USB3_SHIFT) |
328 (SCFG_USBPWRFAULT_DEDICATED <<
329 SCFG_USBPWRFAULT_USB2_SHIFT) |
330 (SCFG_USBPWRFAULT_SHARED <<
331 SCFG_USBPWRFAULT_USB1_SHIFT);
332 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
336 /* We use lpuart0 as system console */
337 uart = QIXIS_READ(brdcfg[14]);
338 uart &= ~CFG_UART_MUX_MASK;
339 uart |= CFG_LPUART_EN << CFG_UART_MUX_SHIFT;
340 QIXIS_WRITE(brdcfg[14], uart);
346 #ifdef CONFIG_FSL_DEEP_SLEEP
347 /* determine if it is a warm boot */
348 bool is_warm_boot(void)
350 #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3)
351 struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR;
353 if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR)
360 int config_board_mux(int ctrl_type)
364 reg14 = QIXIS_READ(brdcfg[14]);
368 reg14 = (reg14 & (~0x6)) | 0x2;
371 puts("Unsupported mux interface type\n");
375 QIXIS_WRITE(brdcfg[14], reg14);
380 int config_serdes_mux(void)
385 #ifdef CONFIG_MISC_INIT_R
386 int misc_init_r(void)
388 if (hwconfig("gpio"))
389 config_board_mux(MUX_TYPE_GPIO);
397 select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT);
399 #ifdef CONFIG_SYS_FSL_SERDES
404 printf("Warning: Adjusting core voltage failed.\n");
406 #ifdef CONFIG_FSL_LS_PPA
410 #ifdef CONFIG_NXP_ESBC
412 * In case of Secure Boot, the IBR configures the SMMU
413 * to allow only Secure transactions.
414 * SMMU must be reset in bypass mode.
415 * Set the ClientPD bit and Clear the USFCFG Bit
418 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
419 out_le32(SMMU_SCR0, val);
420 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
421 out_le32(SMMU_NSCR0, val);
424 #ifdef CONFIG_FSL_CAAM
431 #ifdef CONFIG_OF_BOARD_SETUP
432 int ft_board_setup(void *blob, bd_t *bd)
434 u64 base[CONFIG_NR_DRAM_BANKS];
435 u64 size[CONFIG_NR_DRAM_BANKS];
438 /* fixup DT for the two DDR banks */
439 base[0] = gd->bd->bi_dram[0].start;
440 size[0] = gd->bd->bi_dram[0].size;
441 base[1] = gd->bd->bi_dram[1].start;
442 size[1] = gd->bd->bi_dram[1].size;
444 fdt_fixup_memory_banks(blob, base, size, 2);
445 ft_cpu_setup(blob, bd);
447 #ifdef CONFIG_SYS_DPAA_FMAN
448 fdt_fixup_fman_ethernet(blob);
449 fdt_fixup_board_enet(blob);
452 fdt_fixup_icid(blob);
454 reg = QIXIS_READ(brdcfg[0]);
455 reg = (reg & QIXIS_LBMAP_MASK) >> QIXIS_LBMAP_SHIFT;
457 /* Disable IFC if QSPI is enabled */
459 do_fixup_by_compat(blob, "fsl,ifc",
460 "status", "disabled", 8 + 1, 1);
466 u8 flash_read8(void *addr)
468 return __raw_readb(addr + 1);
471 void flash_write16(u16 val, void *addr)
473 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
475 __raw_writew(shftval, addr);
478 u16 flash_read16(void *addr)
480 u16 val = __raw_readw(addr);
482 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
485 #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH)
486 void *env_sf_get_env_addr(void)
488 return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET);