1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2018-2020 NXP
11 #include <fdt_support.h>
14 #include <fsl_dtsec.h>
16 #include <asm/arch/fsl_serdes.h>
18 #include "../common/qixis.h"
19 #include "../common/fman.h"
20 #include "ls1046aqds_qixis.h"
29 static int mdio_mux[NUM_FM_PORTS];
31 static const char * const mdio_names[] = {
32 "LS1046AQDS_MDIO_RGMII1",
33 "LS1046AQDS_MDIO_RGMII2",
34 "LS1046AQDS_MDIO_SLOT1",
35 "LS1046AQDS_MDIO_SLOT2",
36 "LS1046AQDS_MDIO_SLOT4",
40 /* Map SerDes 1 & 2 lanes to default slot. */
41 static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
43 static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
45 return mdio_names[muxval];
48 struct mii_dev *mii_dev_for_muxval(u8 muxval)
53 if (muxval > EMI1_SLOT4)
56 name = ls1046aqds_mdio_name_for_muxval(muxval);
59 printf("No bus for muxval %x\n", muxval);
63 bus = miiphy_get_dev_by_name(name);
66 printf("No bus by name %s\n", name);
73 struct ls1046aqds_mdio {
75 struct mii_dev *realbus;
78 static void ls1046aqds_mux_mdio(u8 muxval)
83 brdcfg4 = QIXIS_READ(brdcfg[4]);
84 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
85 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
86 QIXIS_WRITE(brdcfg[4], brdcfg4);
90 static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
93 struct ls1046aqds_mdio *priv = bus->priv;
95 ls1046aqds_mux_mdio(priv->muxval);
97 return priv->realbus->read(priv->realbus, addr, devad, regnum);
100 static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
101 int regnum, u16 value)
103 struct ls1046aqds_mdio *priv = bus->priv;
105 ls1046aqds_mux_mdio(priv->muxval);
107 return priv->realbus->write(priv->realbus, addr, devad,
111 static int ls1046aqds_mdio_reset(struct mii_dev *bus)
113 struct ls1046aqds_mdio *priv = bus->priv;
115 return priv->realbus->reset(priv->realbus);
118 static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
120 struct ls1046aqds_mdio *pmdio;
121 struct mii_dev *bus = mdio_alloc();
124 printf("Failed to allocate ls1046aqds MDIO bus\n");
128 pmdio = malloc(sizeof(*pmdio));
130 printf("Failed to allocate ls1046aqds private data\n");
135 bus->read = ls1046aqds_mdio_read;
136 bus->write = ls1046aqds_mdio_write;
137 bus->reset = ls1046aqds_mdio_reset;
138 sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
140 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
142 if (!pmdio->realbus) {
143 printf("No bus with name %s\n", realbusname);
149 pmdio->muxval = muxval;
151 return mdio_register(bus);
154 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
155 enum fm_port port, int offset)
157 struct fixed_link f_link;
160 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
163 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
166 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
169 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
172 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
175 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
180 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
181 /* 2.5G SGMII interface */
182 f_link.phy_id = cpu_to_fdt32(port);
183 f_link.duplex = cpu_to_fdt32(1);
184 f_link.link_speed = cpu_to_fdt32(1000);
186 f_link.asym_pause = 0;
187 /* no PHY for 2.5G SGMII on QDS */
188 fdt_delprop(fdt, offset, "phy-handle");
189 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
190 fdt_setprop_string(fdt, offset, "phy-connection-type",
192 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
195 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
198 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
201 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
204 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
209 fdt_delprop(fdt, offset, "phy-connection-type");
210 fdt_setprop_string(fdt, offset, "phy-connection-type",
212 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
213 (port == FM1_10GEC1 || port == FM1_10GEC2)) {
214 phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
215 if (is_backplane_mode(phyconn)) {
216 /* Backplane KR mode: skip fixups */
217 printf("Interface %d in backplane KR mode\n", port);
220 f_link.phy_id = cpu_to_fdt32(port);
221 f_link.duplex = cpu_to_fdt32(1);
222 f_link.link_speed = cpu_to_fdt32(10000);
224 f_link.asym_pause = 0;
226 fdt_delprop(fdt, offset, "phy-handle");
227 fdt_setprop(fdt, offset, "fixed-link", &f_link,
229 fdt_setprop_string(fdt, offset, "phy-connection-type",
235 void fdt_fixup_board_enet(void *fdt)
239 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
240 switch (fm_info_get_enet_if(i)) {
241 case PHY_INTERFACE_MODE_SGMII:
242 case PHY_INTERFACE_MODE_QSGMII:
243 switch (mdio_mux[i]) {
245 fdt_status_okay_by_alias(fdt, "emi1-slot1");
248 fdt_status_okay_by_alias(fdt, "emi1-slot2");
251 fdt_status_okay_by_alias(fdt, "emi1-slot4");
263 int board_eth_init(bd_t *bis)
265 #ifdef CONFIG_FMAN_ENET
266 int i, idx, lane, slot, interface;
267 struct memac_mdio_info dtsec_mdio_info;
268 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
269 u32 srds_s1, srds_s2;
272 srds_s1 = in_be32(&gur->rcwsr[4]) &
273 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
274 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
276 srds_s2 = in_be32(&gur->rcwsr[4]) &
277 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
278 srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
280 /* Initialize the mdio_mux array so we can recognize empty elements */
281 for (i = 0; i < NUM_FM_PORTS; i++)
282 mdio_mux[i] = EMI_NONE;
284 dtsec_mdio_info.regs =
285 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
287 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
289 /* Register the 1G MDIO bus */
290 fm_memac_mdio_init(bis, &dtsec_mdio_info);
292 /* Register the muxing front-ends to the MDIO buses */
293 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
294 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
295 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
296 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
297 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
299 /* Set the two on-board RGMII PHY address */
300 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
301 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
305 /* SGMII on slot 1, MAC 9 */
306 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
309 /* SGMII on slot 1, MAC 10 */
310 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
313 /* SGMII on slot 1, MAC 5/6 */
314 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
315 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
319 /* QSGMII on lane B, MAC 6/5/10/1 */
320 fm_info_set_phy_address(FM1_DTSEC6,
321 QSGMII_CARD_PORT1_PHY_ADDR_S2);
322 fm_info_set_phy_address(FM1_DTSEC5,
323 QSGMII_CARD_PORT2_PHY_ADDR_S2);
324 fm_info_set_phy_address(FM1_DTSEC10,
325 QSGMII_CARD_PORT3_PHY_ADDR_S2);
326 fm_info_set_phy_address(FM1_DTSEC1,
327 QSGMII_CARD_PORT4_PHY_ADDR_S2);
330 /* SGMII on slot 1, MAC 9/10 */
331 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
332 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
336 /* SGMII on slot 1, MAC 6 */
337 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
340 printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
345 if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
346 /* SGMII on slot 4, MAC 2 */
347 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
349 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
350 idx = i - FM1_DTSEC1;
351 interface = fm_info_get_enet_if(i);
353 case PHY_INTERFACE_MODE_SGMII:
354 case PHY_INTERFACE_MODE_QSGMII:
355 if (interface == PHY_INTERFACE_MODE_SGMII) {
356 if (i == FM1_DTSEC5) {
357 /* route lane 2 to slot1 so to have
358 * one sgmii riser card supports
361 brdcfg12 = QIXIS_READ(brdcfg[12]);
362 QIXIS_WRITE(brdcfg[12],
365 lane = serdes_get_first_lane(FSL_SRDS_1,
366 SGMII_FM1_DTSEC1 + idx);
368 /* clear the bit 7 to route lane B on slot2. */
369 brdcfg12 = QIXIS_READ(brdcfg[12]);
370 QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
372 lane = serdes_get_first_lane(FSL_SRDS_1,
374 lane_to_slot[lane] = 2;
383 slot = lane_to_slot[lane];
384 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
386 if (QIXIS_READ(present2) & (1 << (slot - 1)))
391 mdio_mux[i] = EMI1_SLOT1;
392 fm_info_set_mdio(i, mii_dev_for_muxval(
396 mdio_mux[i] = EMI1_SLOT2;
397 fm_info_set_mdio(i, mii_dev_for_muxval(
401 mdio_mux[i] = EMI1_SLOT4;
402 fm_info_set_mdio(i, mii_dev_for_muxval(
409 case PHY_INTERFACE_MODE_RGMII:
410 case PHY_INTERFACE_MODE_RGMII_TXID:
412 mdio_mux[i] = EMI1_RGMII1;
413 else if (i == FM1_DTSEC4)
414 mdio_mux[i] = EMI1_RGMII2;
415 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
423 #endif /* CONFIG_FMAN_ENET */
425 return pci_eth_init(bis);