1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2016 Freescale Semiconductor, Inc.
4 * Copyright 2018-2020 NXP
10 #include <fdt_support.h>
13 #include <fsl_dtsec.h>
15 #include <asm/arch/fsl_serdes.h>
17 #include "../common/qixis.h"
18 #include "../common/fman.h"
19 #include "ls1046aqds_qixis.h"
28 static int mdio_mux[NUM_FM_PORTS];
30 static const char * const mdio_names[] = {
31 "LS1046AQDS_MDIO_RGMII1",
32 "LS1046AQDS_MDIO_RGMII2",
33 "LS1046AQDS_MDIO_SLOT1",
34 "LS1046AQDS_MDIO_SLOT2",
35 "LS1046AQDS_MDIO_SLOT4",
39 /* Map SerDes 1 & 2 lanes to default slot. */
40 static u8 lane_to_slot[] = {1, 1, 1, 1, 0, 4, 0 , 0};
42 static const char *ls1046aqds_mdio_name_for_muxval(u8 muxval)
44 return mdio_names[muxval];
47 struct mii_dev *mii_dev_for_muxval(u8 muxval)
52 if (muxval > EMI1_SLOT4)
55 name = ls1046aqds_mdio_name_for_muxval(muxval);
58 printf("No bus for muxval %x\n", muxval);
62 bus = miiphy_get_dev_by_name(name);
65 printf("No bus by name %s\n", name);
72 struct ls1046aqds_mdio {
74 struct mii_dev *realbus;
77 static void ls1046aqds_mux_mdio(u8 muxval)
82 brdcfg4 = QIXIS_READ(brdcfg[4]);
83 brdcfg4 &= ~BRDCFG4_EMISEL_MASK;
84 brdcfg4 |= (muxval << BRDCFG4_EMISEL_SHIFT);
85 QIXIS_WRITE(brdcfg[4], brdcfg4);
89 static int ls1046aqds_mdio_read(struct mii_dev *bus, int addr, int devad,
92 struct ls1046aqds_mdio *priv = bus->priv;
94 ls1046aqds_mux_mdio(priv->muxval);
96 return priv->realbus->read(priv->realbus, addr, devad, regnum);
99 static int ls1046aqds_mdio_write(struct mii_dev *bus, int addr, int devad,
100 int regnum, u16 value)
102 struct ls1046aqds_mdio *priv = bus->priv;
104 ls1046aqds_mux_mdio(priv->muxval);
106 return priv->realbus->write(priv->realbus, addr, devad,
110 static int ls1046aqds_mdio_reset(struct mii_dev *bus)
112 struct ls1046aqds_mdio *priv = bus->priv;
114 return priv->realbus->reset(priv->realbus);
117 static int ls1046aqds_mdio_init(char *realbusname, u8 muxval)
119 struct ls1046aqds_mdio *pmdio;
120 struct mii_dev *bus = mdio_alloc();
123 printf("Failed to allocate ls1046aqds MDIO bus\n");
127 pmdio = malloc(sizeof(*pmdio));
129 printf("Failed to allocate ls1046aqds private data\n");
134 bus->read = ls1046aqds_mdio_read;
135 bus->write = ls1046aqds_mdio_write;
136 bus->reset = ls1046aqds_mdio_reset;
137 sprintf(bus->name, ls1046aqds_mdio_name_for_muxval(muxval));
139 pmdio->realbus = miiphy_get_dev_by_name(realbusname);
141 if (!pmdio->realbus) {
142 printf("No bus with name %s\n", realbusname);
148 pmdio->muxval = muxval;
150 return mdio_register(bus);
153 void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr,
154 enum fm_port port, int offset)
156 struct fixed_link f_link;
159 if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII) {
162 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p1");
165 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p2");
168 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p3");
171 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s1-p4");
174 fdt_set_phy_handle(fdt, compat, addr, "sgmii-s4-p1");
179 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_SGMII_2500) {
180 /* 2.5G SGMII interface */
181 f_link.phy_id = cpu_to_fdt32(port);
182 f_link.duplex = cpu_to_fdt32(1);
183 f_link.link_speed = cpu_to_fdt32(1000);
185 f_link.asym_pause = 0;
186 /* no PHY for 2.5G SGMII on QDS */
187 fdt_delprop(fdt, offset, "phy-handle");
188 fdt_setprop(fdt, offset, "fixed-link", &f_link, sizeof(f_link));
189 fdt_setprop_string(fdt, offset, "phy-connection-type",
191 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_QSGMII) {
194 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p4");
197 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p2");
200 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p1");
203 fdt_set_phy_handle(fdt, compat, addr, "qsgmii-s2-p3");
208 fdt_delprop(fdt, offset, "phy-connection-type");
209 fdt_setprop_string(fdt, offset, "phy-connection-type",
211 } else if (fm_info_get_enet_if(port) == PHY_INTERFACE_MODE_XGMII &&
212 (port == FM1_10GEC1 || port == FM1_10GEC2)) {
213 phyconn = fdt_getprop(fdt, offset, "phy-connection-type", NULL);
214 if (is_backplane_mode(phyconn)) {
215 /* Backplane KR mode: skip fixups */
216 printf("Interface %d in backplane KR mode\n", port);
219 f_link.phy_id = cpu_to_fdt32(port);
220 f_link.duplex = cpu_to_fdt32(1);
221 f_link.link_speed = cpu_to_fdt32(10000);
223 f_link.asym_pause = 0;
225 fdt_delprop(fdt, offset, "phy-handle");
226 fdt_setprop(fdt, offset, "fixed-link", &f_link,
228 fdt_setprop_string(fdt, offset, "phy-connection-type",
234 void fdt_fixup_board_enet(void *fdt)
238 for (i = FM1_DTSEC1; i < NUM_FM_PORTS; i++) {
239 switch (fm_info_get_enet_if(i)) {
240 case PHY_INTERFACE_MODE_SGMII:
241 case PHY_INTERFACE_MODE_QSGMII:
242 switch (mdio_mux[i]) {
244 fdt_status_okay_by_alias(fdt, "emi1-slot1");
247 fdt_status_okay_by_alias(fdt, "emi1-slot2");
250 fdt_status_okay_by_alias(fdt, "emi1-slot4");
262 int board_eth_init(bd_t *bis)
264 #ifdef CONFIG_FMAN_ENET
265 int i, idx, lane, slot, interface;
266 struct memac_mdio_info dtsec_mdio_info;
267 struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
268 u32 srds_s1, srds_s2;
271 srds_s1 = in_be32(&gur->rcwsr[4]) &
272 FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK;
273 srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT;
275 srds_s2 = in_be32(&gur->rcwsr[4]) &
276 FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK;
277 srds_s2 >>= FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT;
279 /* Initialize the mdio_mux array so we can recognize empty elements */
280 for (i = 0; i < NUM_FM_PORTS; i++)
281 mdio_mux[i] = EMI_NONE;
283 dtsec_mdio_info.regs =
284 (struct memac_mdio_controller *)CONFIG_SYS_FM1_DTSEC_MDIO_ADDR;
286 dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
288 /* Register the 1G MDIO bus */
289 fm_memac_mdio_init(bis, &dtsec_mdio_info);
291 /* Register the muxing front-ends to the MDIO buses */
292 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII1);
293 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_RGMII2);
294 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT1);
295 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT2);
296 ls1046aqds_mdio_init(DEFAULT_FM_MDIO_NAME, EMI1_SLOT4);
298 /* Set the two on-board RGMII PHY address */
299 fm_info_set_phy_address(FM1_DTSEC3, RGMII_PHY1_ADDR);
300 fm_info_set_phy_address(FM1_DTSEC4, RGMII_PHY2_ADDR);
304 /* SGMII on slot 1, MAC 9 */
305 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
308 /* SGMII on slot 1, MAC 10 */
309 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
312 /* SGMII on slot 1, MAC 5/6 */
313 fm_info_set_phy_address(FM1_DTSEC5, SGMII_CARD_PORT3_PHY_ADDR);
314 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
318 /* QSGMII on lane B, MAC 6/5/10/1 */
319 fm_info_set_phy_address(FM1_DTSEC6,
320 QSGMII_CARD_PORT1_PHY_ADDR_S2);
321 fm_info_set_phy_address(FM1_DTSEC5,
322 QSGMII_CARD_PORT2_PHY_ADDR_S2);
323 fm_info_set_phy_address(FM1_DTSEC10,
324 QSGMII_CARD_PORT3_PHY_ADDR_S2);
325 fm_info_set_phy_address(FM1_DTSEC1,
326 QSGMII_CARD_PORT4_PHY_ADDR_S2);
329 /* SGMII on slot 1, MAC 9/10 */
330 fm_info_set_phy_address(FM1_DTSEC9, SGMII_CARD_PORT1_PHY_ADDR);
331 fm_info_set_phy_address(FM1_DTSEC10, SGMII_CARD_PORT2_PHY_ADDR);
335 /* SGMII on slot 1, MAC 6 */
336 fm_info_set_phy_address(FM1_DTSEC6, SGMII_CARD_PORT4_PHY_ADDR);
339 printf("Invalid SerDes protocol 0x%x for LS1046AQDS\n",
344 if (srds_s2 == 0x5a59 || srds_s2 == 0x5a06)
345 /* SGMII on slot 4, MAC 2 */
346 fm_info_set_phy_address(FM1_DTSEC2, SGMII_CARD_PORT1_PHY_ADDR);
348 for (i = FM1_DTSEC1; i < FM1_DTSEC1 + CONFIG_SYS_NUM_FM1_DTSEC; i++) {
349 idx = i - FM1_DTSEC1;
350 interface = fm_info_get_enet_if(i);
352 case PHY_INTERFACE_MODE_SGMII:
353 case PHY_INTERFACE_MODE_QSGMII:
354 if (interface == PHY_INTERFACE_MODE_SGMII) {
355 if (i == FM1_DTSEC5) {
356 /* route lane 2 to slot1 so to have
357 * one sgmii riser card supports
360 brdcfg12 = QIXIS_READ(brdcfg[12]);
361 QIXIS_WRITE(brdcfg[12],
364 lane = serdes_get_first_lane(FSL_SRDS_1,
365 SGMII_FM1_DTSEC1 + idx);
367 /* clear the bit 7 to route lane B on slot2. */
368 brdcfg12 = QIXIS_READ(brdcfg[12]);
369 QIXIS_WRITE(brdcfg[12], brdcfg12 & 0x7f);
371 lane = serdes_get_first_lane(FSL_SRDS_1,
373 lane_to_slot[lane] = 2;
382 slot = lane_to_slot[lane];
383 debug("FM1@DTSEC%u expects SGMII in slot %u\n",
385 if (QIXIS_READ(present2) & (1 << (slot - 1)))
390 mdio_mux[i] = EMI1_SLOT1;
391 fm_info_set_mdio(i, mii_dev_for_muxval(
395 mdio_mux[i] = EMI1_SLOT2;
396 fm_info_set_mdio(i, mii_dev_for_muxval(
400 mdio_mux[i] = EMI1_SLOT4;
401 fm_info_set_mdio(i, mii_dev_for_muxval(
408 case PHY_INTERFACE_MODE_RGMII:
409 case PHY_INTERFACE_MODE_RGMII_TXID:
411 mdio_mux[i] = EMI1_RGMII1;
412 else if (i == FM1_DTSEC4)
413 mdio_mux[i] = EMI1_RGMII2;
414 fm_info_set_mdio(i, mii_dev_for_muxval(mdio_mux[i]));
422 #endif /* CONFIG_FMAN_ENET */
424 return pci_eth_init(bis);