2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
29 DECLARE_GLOBAL_DATA_PTR;
33 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
34 #ifndef CONFIG_SD_BOOT
35 u8 cfg_rcw_src1, cfg_rcw_src2;
40 printf("Board: LS1043ARDB, boot from ");
45 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
46 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
47 cpld_rev_bit(&cfg_rcw_src1);
48 cfg_rcw_src = cfg_rcw_src1;
49 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
51 if (cfg_rcw_src == 0x25)
52 printf("vBank %d\n", CPLD_READ(vbank));
53 else if (cfg_rcw_src == 0x106)
56 printf("Invalid setting of SW4\n");
59 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
60 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
62 puts("SERDES Reference Clocks:\n");
63 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
64 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
71 gd->ram_size = initdram(0);
76 int board_early_init_f(void)
78 fsl_lsch2_early_init_f();
86 init_final_memctl_regs();
89 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
90 enable_layerscape_ns_access();
100 int config_board_mux(void)
102 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
105 if (hwconfig("qe-hdlc")) {
106 out_be32(&scfg->rcwpmuxcr0,
107 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
108 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
109 in_be32(&scfg->rcwpmuxcr0));
111 #ifdef CONFIG_HAS_FSL_XHCI_USB
112 out_be32(&scfg->rcwpmuxcr0, 0x3333);
113 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
114 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
115 SCFG_USBPWRFAULT_USB3_SHIFT) |
116 (SCFG_USBPWRFAULT_DEDICATED <<
117 SCFG_USBPWRFAULT_USB2_SHIFT) |
118 (SCFG_USBPWRFAULT_SHARED <<
119 SCFG_USBPWRFAULT_USB1_SHIFT);
120 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
126 #if defined(CONFIG_MISC_INIT_R)
127 int misc_init_r(void)
130 #ifdef CONFIG_SECURE_BOOT
131 /* In case of Secure Boot, the IBR configures the SMMU
132 * to allow only Secure transactions.
133 * SMMU must be reset in bypass mode.
134 * Set the ClientPD bit and Clear the USFCFG Bit
137 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
138 out_le32(SMMU_SCR0, val);
139 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
140 out_le32(SMMU_NSCR0, val);
142 #ifdef CONFIG_FSL_CAAM
149 void fdt_del_qe(void *blob)
153 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
155 fdt_del_node(blob, nodeoff);
159 int ft_board_setup(void *blob, bd_t *bd)
161 u64 base[CONFIG_NR_DRAM_BANKS];
162 u64 size[CONFIG_NR_DRAM_BANKS];
164 /* fixup DT for the two DDR banks */
165 base[0] = gd->bd->bi_dram[0].start;
166 size[0] = gd->bd->bi_dram[0].size;
167 base[1] = gd->bd->bi_dram[1].start;
168 size[1] = gd->bd->bi_dram[1].size;
170 fdt_fixup_memory_banks(blob, base, size, 2);
171 ft_cpu_setup(blob, bd);
173 #ifdef CONFIG_SYS_DPAA_FMAN
174 fdt_fixup_fman_ethernet(blob);
178 * qe-hdlc and usb multi-use the pins,
179 * when set hwconfig to qe-hdlc, delete usb node.
181 if (hwconfig("qe-hdlc"))
182 #ifdef CONFIG_HAS_FSL_XHCI_USB
183 fdt_del_node_and_alias(blob, "usb1");
186 * qe just support qe-uart and qe-hdlc,
187 * if qe-uart and qe-hdlc are not set in hwconfig,
190 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
196 u8 flash_read8(void *addr)
198 return __raw_readb(addr + 1);
201 void flash_write16(u16 val, void *addr)
203 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
205 __raw_writew(shftval, addr);
208 u16 flash_read16(void *addr)
210 u16 val = __raw_readw(addr);
212 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);