board/freescale/ls1043ardb/ls1043ardb.c

   1 /*
   2  * Copyright 2015 Freescale Semiconductor, Inc.
   3  *
   4  * SPDX-License-Identifier:     GPL-2.0+
   5  */
   6
   7 #include <common.h>
   8 #include <i2c.h>
   9 #include <asm/io.h>
  10 #include <asm/arch/clock.h>
  11 #include <asm/arch/fsl_serdes.h>
  12 #include <asm/arch/soc.h>
  13 #include <hwconfig.h>
  14 #include <ahci.h>
  15 #include <mmc.h>
  16 #include <scsi.h>
  17 #include <fm_eth.h>
  18 #include <fsl_csu.h>
  19 #include <fsl_esdhc.h>
  20 #include <fsl_ifc.h>
  21 #include <environment.h>
  22 #include <fsl_sec.h>
  23 #include "cpld.h"
  24 #ifdef CONFIG_U_QE
  25 #include <fsl_qe.h>
  26 #endif
  27
  28
  29 DECLARE_GLOBAL_DATA_PTR;
  30
  31 int checkboard(void)
  32 {
  33         static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
  34 #ifndef CONFIG_SD_BOOT
  35         u8 cfg_rcw_src1, cfg_rcw_src2;
  36         u32 cfg_rcw_src;
  37 #endif
  38         u32 sd1refclk_sel;
  39
  40         printf("Board: LS1043ARDB, boot from ");
  41
  42 #ifdef CONFIG_SD_BOOT
  43         puts("SD\n");
  44 #else
  45         cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
  46         cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
  47         cpld_rev_bit(&cfg_rcw_src1);
  48         cfg_rcw_src = cfg_rcw_src1;
  49         cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
  50
  51         if (cfg_rcw_src == 0x25)
  52                 printf("vBank %d\n", CPLD_READ(vbank));
  53         else if (cfg_rcw_src == 0x106)
  54                 puts("NAND\n");
  55         else
  56                 printf("Invalid setting of SW4\n");
  57 #endif
  58
  59         printf("CPLD:  V%x.%x\nPCBA:  V%x.0\n", CPLD_READ(cpld_ver),
  60                CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
  61
  62         puts("SERDES Reference Clocks:\n");
  63         sd1refclk_sel = CPLD_READ(sd1refclk_sel);
  64         printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
  65
  66         return 0;
  67 }
  68
  69 int dram_init(void)
  70 {
  71         gd->ram_size = initdram(0);
  72
  73         return 0;
  74 }
  75
  76 int board_early_init_f(void)
  77 {
  78         fsl_lsch2_early_init_f();
  79
  80         return 0;
  81 }
  82
  83 int board_init(void)
  84 {
  85         struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
  86
  87         /*
  88          * Set CCI-400 control override register to enable barrier
  89          * transaction
  90          */
  91         out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
  92
  93 #ifdef CONFIG_FSL_IFC
  94         init_final_memctl_regs();
  95 #endif
  96
  97 #ifdef CONFIG_ENV_IS_NOWHERE
  98         gd->env_addr = (ulong)&default_environment[0];
  99 #endif
 100
 101 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
 102         enable_layerscape_ns_access();
 103 #endif
 104
 105 #ifdef CONFIG_U_QE
 106         u_qe_init();
 107 #endif
 108
 109         return 0;
 110 }
 111
 112 int config_board_mux(void)
 113 {
 114         struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
 115         u32 usb_pwrfault;
 116
 117         if (hwconfig("qe-hdlc")) {
 118                 out_be32(&scfg->rcwpmuxcr0,
 119                          (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
 120                 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
 121                        in_be32(&scfg->rcwpmuxcr0));
 122         } else {
 123 #ifdef CONFIG_HAS_FSL_XHCI_USB
 124                 out_be32(&scfg->rcwpmuxcr0, 0x3333);
 125                 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
 126                 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
 127                                 SCFG_USBPWRFAULT_USB3_SHIFT) |
 128                                 (SCFG_USBPWRFAULT_DEDICATED <<
 129                                 SCFG_USBPWRFAULT_USB2_SHIFT) |
 130                                 (SCFG_USBPWRFAULT_SHARED <<
 131                                  SCFG_USBPWRFAULT_USB1_SHIFT);
 132                 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
 133 #endif
 134         }
 135         return 0;
 136 }
 137
 138 #if defined(CONFIG_MISC_INIT_R)
 139 int misc_init_r(void)
 140 {
 141         config_board_mux();
 142 #ifdef CONFIG_SECURE_BOOT
 143         /* In case of Secure Boot, the IBR configures the SMMU
 144          * to allow only Secure transactions.
 145          * SMMU must be reset in bypass mode.
 146          * Set the ClientPD bit and Clear the USFCFG Bit
 147          */
 148         u32 val;
 149         val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 150         out_le32(SMMU_SCR0, val);
 151         val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
 152         out_le32(SMMU_NSCR0, val);
 153 #endif
 154 #ifdef CONFIG_FSL_CAAM
 155         return sec_init();
 156 #endif
 157         return 0;
 158 }
 159 #endif
 160
 161 void fdt_del_qe(void *blob)
 162 {
 163         int nodeoff = 0;
 164
 165         while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
 166                                 "fsl,qe")) >= 0) {
 167                 fdt_del_node(blob, nodeoff);
 168         }
 169 }
 170
 171 int ft_board_setup(void *blob, bd_t *bd)
 172 {
 173         u64 base[CONFIG_NR_DRAM_BANKS];
 174         u64 size[CONFIG_NR_DRAM_BANKS];
 175
 176         /* fixup DT for the two DDR banks */
 177         base[0] = gd->bd->bi_dram[0].start;
 178         size[0] = gd->bd->bi_dram[0].size;
 179         base[1] = gd->bd->bi_dram[1].start;
 180         size[1] = gd->bd->bi_dram[1].size;
 181
 182         fdt_fixup_memory_banks(blob, base, size, 2);
 183         ft_cpu_setup(blob, bd);
 184
 185 #ifdef CONFIG_SYS_DPAA_FMAN
 186         fdt_fixup_fman_ethernet(blob);
 187 #endif
 188
 189         /*
 190          * qe-hdlc and usb multi-use the pins,
 191          * when set hwconfig to qe-hdlc, delete usb node.
 192          */
 193         if (hwconfig("qe-hdlc"))
 194 #ifdef CONFIG_HAS_FSL_XHCI_USB
 195                 fdt_del_node_and_alias(blob, "usb1");
 196 #endif
 197         /*
 198          * qe just support qe-uart and qe-hdlc,
 199          * if qe-uart and qe-hdlc are not set in hwconfig,
 200          * delete qe node.
 201          */
 202         if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
 203                 fdt_del_qe(blob);
 204
 205         return 0;
 206 }
 207
 208 u8 flash_read8(void *addr)
 209 {
 210         return __raw_readb(addr + 1);
 211 }
 212
 213 void flash_write16(u16 val, void *addr)
 214 {
 215         u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
 216
 217         __raw_writew(shftval, addr);
 218 }
 219
 220 u16 flash_read16(void *addr)
 221 {
 222         u16 val = __raw_readw(addr);
 223
 224         return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);
 225 }