1 // SPDX-License-Identifier: GPL-2.0+
3 * Copyright 2015 Freescale Semiconductor, Inc.
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
13 #include <asm/arch-fsl-layerscape/fsl_icid.h>
14 #include <fdt_support.h>
20 #include <fsl_esdhc.h>
27 #include <asm/arch/ppa.h>
29 DECLARE_GLOBAL_DATA_PTR;
32 struct ifc_regs ifc_cfg_nor_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
36 CONFIG_SYS_NOR_CSPR_EXT,
50 CONFIG_SYS_NAND_CSPR_EXT,
51 CONFIG_SYS_NAND_AMASK,
54 CONFIG_SYS_NAND_FTIM0,
55 CONFIG_SYS_NAND_FTIM1,
56 CONFIG_SYS_NAND_FTIM2,
63 CONFIG_SYS_CPLD_CSPR_EXT,
64 CONFIG_SYS_CPLD_AMASK,
67 CONFIG_SYS_CPLD_FTIM0,
68 CONFIG_SYS_CPLD_FTIM1,
69 CONFIG_SYS_CPLD_FTIM2,
75 struct ifc_regs ifc_cfg_nand_boot[CONFIG_SYS_FSL_IFC_BANK_COUNT] = {
79 CONFIG_SYS_NAND_CSPR_EXT,
80 CONFIG_SYS_NAND_AMASK,
83 CONFIG_SYS_NAND_FTIM0,
84 CONFIG_SYS_NAND_FTIM1,
85 CONFIG_SYS_NAND_FTIM2,
92 CONFIG_SYS_NOR_CSPR_EXT,
104 CONFIG_SYS_CPLD_CSPR,
105 CONFIG_SYS_CPLD_CSPR_EXT,
106 CONFIG_SYS_CPLD_AMASK,
107 CONFIG_SYS_CPLD_CSOR,
109 CONFIG_SYS_CPLD_FTIM0,
110 CONFIG_SYS_CPLD_FTIM1,
111 CONFIG_SYS_CPLD_FTIM2,
112 CONFIG_SYS_CPLD_FTIM3
117 void ifc_cfg_boot_info(struct ifc_regs_info *regs_info)
119 enum boot_src src = get_boot_src();
121 if (src == BOOT_SOURCE_IFC_NAND)
122 regs_info->regs = ifc_cfg_nand_boot;
124 regs_info->regs = ifc_cfg_nor_boot;
125 regs_info->cs_size = CONFIG_SYS_FSL_IFC_BANK_COUNT;
129 int board_early_init_f(void)
131 fsl_lsch2_early_init_f();
136 #ifndef CONFIG_SPL_BUILD
140 #ifdef CONFIG_TFABOOT
141 enum boot_src src = get_boot_src();
143 static const char *freq[2] = {"100.00MHZ", "156.25MHZ"};
144 #ifndef CONFIG_SD_BOOT
145 u8 cfg_rcw_src1, cfg_rcw_src2;
150 printf("Board: LS1043ARDB, boot from ");
152 #ifdef CONFIG_TFABOOT
153 if (src == BOOT_SOURCE_SD_MMC)
158 #ifdef CONFIG_SD_BOOT
161 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
162 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
163 cpld_rev_bit(&cfg_rcw_src1);
164 cfg_rcw_src = cfg_rcw_src1;
165 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
167 if (cfg_rcw_src == 0x25)
168 printf("vBank %d\n", CPLD_READ(vbank));
169 else if (cfg_rcw_src == 0x106)
172 printf("Invalid setting of SW4\n");
175 #ifdef CONFIG_TFABOOT
178 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
179 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
181 puts("SERDES Reference Clocks:\n");
182 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
183 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
190 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
192 #ifdef CONFIG_SYS_FSL_ERRATUM_A010315
196 #ifdef CONFIG_FSL_IFC
197 init_final_memctl_regs();
200 #ifdef CONFIG_NXP_ESBC
201 /* In case of Secure Boot, the IBR configures the SMMU
202 * to allow only Secure transactions.
203 * SMMU must be reset in bypass mode.
204 * Set the ClientPD bit and Clear the USFCFG Bit
207 val = (in_le32(SMMU_SCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
208 out_le32(SMMU_SCR0, val);
209 val = (in_le32(SMMU_NSCR0) | SCR0_CLIENTPD_MASK) & ~(SCR0_USFCFG_MASK);
210 out_le32(SMMU_NSCR0, val);
213 #ifdef CONFIG_FSL_CAAM
217 #ifdef CONFIG_FSL_LS_PPA
224 /* invert AQR105 IRQ pins polarity */
225 out_be32(&scfg->intpcr, AQR105_IRQ_MASK);
230 int config_board_mux(void)
232 struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR;
235 if (hwconfig("qe-hdlc")) {
236 out_be32(&scfg->rcwpmuxcr0,
237 (in_be32(&scfg->rcwpmuxcr0) & ~0xff00) | 0x6600);
238 printf("Assign to qe-hdlc clk, rcwpmuxcr0=%x\n",
239 in_be32(&scfg->rcwpmuxcr0));
241 #ifdef CONFIG_HAS_FSL_XHCI_USB
242 out_be32(&scfg->rcwpmuxcr0, 0x3333);
243 out_be32(&scfg->usbdrvvbus_selcr, SCFG_USBDRVVBUS_SELCR_USB1);
244 usb_pwrfault = (SCFG_USBPWRFAULT_DEDICATED <<
245 SCFG_USBPWRFAULT_USB3_SHIFT) |
246 (SCFG_USBPWRFAULT_DEDICATED <<
247 SCFG_USBPWRFAULT_USB2_SHIFT) |
248 (SCFG_USBPWRFAULT_SHARED <<
249 SCFG_USBPWRFAULT_USB1_SHIFT);
250 out_be32(&scfg->usbpwrfault_selcr, usb_pwrfault);
256 #if defined(CONFIG_MISC_INIT_R)
257 int misc_init_r(void)
264 void fdt_del_qe(void *blob)
268 while ((nodeoff = fdt_node_offset_by_compatible(blob, 0,
270 fdt_del_node(blob, nodeoff);
274 int ft_board_setup(void *blob, bd_t *bd)
276 u64 base[CONFIG_NR_DRAM_BANKS];
277 u64 size[CONFIG_NR_DRAM_BANKS];
279 /* fixup DT for the two DDR banks */
280 base[0] = gd->bd->bi_dram[0].start;
281 size[0] = gd->bd->bi_dram[0].size;
282 base[1] = gd->bd->bi_dram[1].start;
283 size[1] = gd->bd->bi_dram[1].size;
285 fdt_fixup_memory_banks(blob, base, size, 2);
286 ft_cpu_setup(blob, bd);
288 #ifdef CONFIG_SYS_DPAA_FMAN
289 #ifndef CONFIG_DM_ETH
290 fdt_fixup_fman_ethernet(blob);
294 fdt_fixup_icid(blob);
297 * qe-hdlc and usb multi-use the pins,
298 * when set hwconfig to qe-hdlc, delete usb node.
300 if (hwconfig("qe-hdlc"))
301 #ifdef CONFIG_HAS_FSL_XHCI_USB
302 fdt_del_node_and_alias(blob, "usb1");
305 * qe just support qe-uart and qe-hdlc,
306 * if qe-uart and qe-hdlc are not set in hwconfig,
309 if (!hwconfig("qe-uart") && !hwconfig("qe-hdlc"))
315 u8 flash_read8(void *addr)
317 return __raw_readb(addr + 1);
320 void flash_write16(u16 val, void *addr)
322 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
324 __raw_writew(shftval, addr);
327 u16 flash_read16(void *addr)
329 u16 val = __raw_readw(addr);
331 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);