2 * Copyright 2015 Freescale Semiconductor, Inc.
4 * SPDX-License-Identifier: GPL-2.0+
10 #include <asm/arch/clock.h>
11 #include <asm/arch/fsl_serdes.h>
12 #include <asm/arch/soc.h>
19 #include <fsl_esdhc.h>
23 DECLARE_GLOBAL_DATA_PTR;
27 static const char *freq[3] = {"100.00MHZ", "156.25MHZ"};
28 u8 cfg_rcw_src1, cfg_rcw_src2;
32 printf("Board: LS1043ARDB, boot from ");
34 cfg_rcw_src1 = CPLD_READ(cfg_rcw_src1);
35 cfg_rcw_src2 = CPLD_READ(cfg_rcw_src2);
36 cpld_rev_bit(&cfg_rcw_src1);
37 cfg_rcw_src = cfg_rcw_src1;
38 cfg_rcw_src = (cfg_rcw_src << 1) | cfg_rcw_src2;
40 if (cfg_rcw_src == 0x25)
41 printf("vBank %d\n", CPLD_READ(vbank));
42 else if (cfg_rcw_src == 0x106)
45 printf("Invalid setting of SW4\n");
47 printf("CPLD: V%x.%x\nPCBA: V%x.0\n", CPLD_READ(cpld_ver),
48 CPLD_READ(cpld_ver_sub), CPLD_READ(pcba_ver));
50 puts("SERDES Reference Clocks:\n");
51 sd1refclk_sel = CPLD_READ(sd1refclk_sel);
52 printf("SD1_CLK1 = %s, SD1_CLK2 = %s\n", freq[sd1refclk_sel], freq[0]);
59 gd->ram_size = initdram(0);
64 int board_early_init_f(void)
66 fsl_lsch2_early_init_f();
72 struct ccsr_cci400 *cci = (struct ccsr_cci400 *)CONFIG_SYS_CCI400_ADDR;
75 * Set CCI-400 control override register to enable barrier
78 out_le32(&cci->ctrl_ord, CCI400_CTRLORD_EN_BARRIER);
81 init_final_memctl_regs();
84 #ifdef CONFIG_ENV_IS_NOWHERE
85 gd->env_addr = (ulong)&default_environment[0];
88 #ifdef CONFIG_LAYERSCAPE_NS_ACCESS
89 enable_layerscape_ns_access();
95 int config_board_mux(void)
100 #if defined(CONFIG_MISC_INIT_R)
101 int misc_init_r(void)
109 int ft_board_setup(void *blob, bd_t *bd)
111 ft_cpu_setup(blob, bd);
113 #ifdef CONFIG_SYS_DPAA_FMAN
114 fdt_fixup_fman_ethernet(blob);
119 u8 flash_read8(void *addr)
121 return __raw_readb(addr + 1);
124 void flash_write16(u16 val, void *addr)
126 u16 shftval = (((val >> 8) & 0xff) | ((val << 8) & 0xff00));
128 __raw_writew(shftval, addr);
131 u16 flash_read16(void *addr)
133 u16 val = __raw_readw(addr);
135 return (((val) >> 8) & 0x00ff) | (((val) << 8) & 0xff00);